Abstract

In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock; a performance increase of up to 16 times.

Highlights

  • Electronic payment systems are known to use the Triple Data Encryption Standard (TDES) scheme for the encryption/decryption of data, and faster implementations are of great significance

  • Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and faster implementations are of great significance [3] [4]

  • This paper focuses on increasing the performance of TDES, in Electronic Codebook (ECB) mode [6], by implementing a 48-stage pipelined depth design

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Summary

A Fast FPGA Implementation for Triple DES Encryption Scheme

IEEE Network Security Research Lab, Department of Electrical/Computer Engineering, The University of Texas Rio Grande Valley, Edinburg, USA. How to cite this paper: Rosal, E.D. and Kumar, S. (2017) A Fast FPGA Implementation for Triple DES Encryption Scheme. Received: June 18, 2017 Accepted: September 22, 2017 Published: September 25, 2017

Introduction
TDES Pipelined Design
DES Algorithm
DES Decryption Key Scheduler
Key Bank
TDES Design Evaluation
Performance
Performance Comparison
Findings
Conclusions
Full Text
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