고속 고성능 시그마-델타 ADC를 위한 최소왜곡 데시메이션 필터의 설계 및 분석

Abstract

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.