A partial-polyphase VLSI architecture for very high speed CIC decimation filters

Abstract

A partial-polyphase architecture for CIC (Cascaded Integrator-Comb) decimation filters is proposed in this paper. Based on the partial-polyphase decomposition and parallel processing techniques, filters with the new proposed architecture can operate at much lower sampling rate and still achieve the same performance as Hogenauer's CIC filters. With the partial-polyphase decomposition, complicated polyphase decompositions are avoided in the case of decimation ratio and filter order is high. The new architecture has advantages in high speed operation, low power consumption and low complexity for VLSI implementation. Design issues such as polyphase components, internal word length, built-in self-test scheme and layout design considerations have been discussed.