Abstract
This CIC (Cascaded integrator comb) decimation filter is widely applicable to reduce the data sampling rate in DDC (Digital Down Conversion). In this paper, the theory of CIC decimation filter architecture is researched. Based on the idea of software defined radio (SDR), we go forwards a new method to design CIC decimation filter. This method makes use of SOPC (System On Programmer Chip) technology. We use the tool of SOPC Builder to design the CIC decimation filter IP core. Then we design other relevant IP core resources and build a SOPC system. Finally the designed system is downloaded to the SOPC comprehensive experiment testbed. Experimental results show that the designed CIC decimation filter component can be implemented successfully based on FPGA, and the functions of CIC decimation filter component are programmable, reliable and portable.
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