Zynq-7000 Field Programmable Gate Array Research Articles

Hardware and software co-design for detecting hypertension from photoplethysmogram

Hypertension is one of the leading causes of cardiovascular disease morbidity in the world. If remains untreated, it may cause severe damage like heart attack or even death. Early detection is required to prevent the development of other cardiac abnormalities. Photoplethysmogram (PPG) is a bio signal that can be obtained optically by a sensor. It is studied to monitor the change of volume of blood and detect heart conditions. Previous studies have already applied PPG to detect hypertension at the software level. In this article, along with software-based detection, we have implemented a digital hardware-based system for detecting hypertension from signals recorded using PPG sensor. Xilinx ZedBoard Zynq-7000 field programmable gate array (FPGA) board is utilized for designing the embedded system. The hypertension detection accuracy is 98.02% at the software level while for the digital system, it is 96.05% consuming 0.374 W power. The study can be analyzed for other cardiac disease detection and medical equipment development.

FPGA based Flexible Implementation of Light Weight Inference on Deep Convolutional Neural Networks

Standard Convolution (StdConv) is the main technique used in the state of the art Deep Convolutional Neural Networks (DCNNs). Fewer computations are achieved if Depthwise Separable Convolution technique (SepConv) is used as an alternative. A crucial issue in many applications like smart cameras and autonomous vehicles where low latency is essential stems from deploying a lightweight and low cost inference models. An acceptable accuracy should be kept with tolerable computations and memory access load. A flexible architecture for different DCNN convolution types and models is proposed. The flexibility comes from the sharing of one memory access unit with different types of layers regardless of the selected kernel size, by multiplying each weight vector by local operators with variant aperture. Moreover, one depthwise computation unit can be used for both standard and pointwise layers. The learnable parameters are quantized to 8-bits fixed point representation and that gives very limited reduction of accuracy and a considerable reduction of the Field-Programmable Gate Array (FPGA) resources. To reduce processing time, inter layer parallel computations are performed. The experiment is conducted by using grey scale ORL database with shallow Convolutional Neural Network (CNN) and the colored Canadian Institute for Advanced Research 10 classes (CIFAR-10) database with DCNN, and a comparable accuracies of 93% and 85.7% are achieved respectively using very low cost of Spartan 3E and moderate cost of zynq FPGA platforms

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Reconfigurable linear feedback shift register for wireless communication and coding

<p>Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.</p>

High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

For multiple signal-processing applications, estimating the target’s speed, distance, and elevation angle by using applications running in real time and consequently, fast data rates is important. Custom hardwares, such as field programmable gate arrays (FPGAs), are often used to prototype and deploy such signal-processing algorithms. Multiple signal classification (MUSIC) is typically used for direction-of-arrival (DOA) estimation. It involves complex mathematical operations such as covariance matrix computation, eigen value decomposition, and peak value search for signal values. With a novel high-level synthesis (HLS)-based design approach that optimizes the bit widths for the eigen value decomposition logic, this study presents an area and speed-optimal implementation of MUSIC algorithm on FPGA. The final implementation involving the covariance matrix computation, eigen value decomposition, and peak search was implemented on Xilinx Zynq (XC7Z020) FPGA. Because of its optimum bit widths, area utilization was minimized and operation frequency on the target FPGA was maximized. The proposed design works in real time to estimate the DOA in less than 1.7 µs (15 % faster than reported values) and uses up to 30 % less resources on the target FPGA compared with other reported implementations.

RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RT-libSGM runs more than 2× faster at a much lower energy cost.

FPGA Implementation of Extended Kalman Filter for Parameters Estimation of Railway Wheelset

It is necessary to know the status of adhesion conditions between wheel and rail for efficient accelerating and decelerating of railroad vehicle. The proper estimation of adhesion conditions and their real-time implementation is considered a challenge for scholars. In this paper, the development of simulation model of extended Kalman filter (EKF) in MATLAB/Simulink is presented to estimate various railway wheelset parameters in different contact conditions of track. Due to concurrent in nature, the Xilinx® System-on-Chip Zynq Field Programmable Gate Array (FPGA) device is chosen to check the onboard estimation of wheel-rail interaction parameters by using the National Instruments (NI) myRIO® development board. The NI myRIO® development board is flexible to deal with nonlinearities, uncertain changes, and fast-changing dynamics in real-time occurring in wheel-rail contact conditions during vehicle operation. The simulated dataset of the railway nonlinear wheelset model is tested on FPGA-based EKF with different track conditions and with accelerating and decelerating operations of the vehicle. The proposed model-based estimation of railway wheelset parameters is synthesized on FPGA and its simulation is carried out for functional verification on FPGA. The obtained simulation results are aligned with the simulation results obtained through MATLAB. To the best of our knowledge, this is the first time study that presents the implementation of a model-based estimation of railway wheelset parameters on FPGA and its functional verification. The functional behavior of the FPGA-based estimator shows that these results are the addition of current knowledge in the field of the railway.

FPGA-Based Implementation for Real-Time Epileptic EEG Classification Using Hjorth Descriptor and KNN

The EEG is one of the main medical instruments used by clinicians in the analysis and diagnosis of epilepsy through visual observations or computers. Visual inspection is difficult, time-consuming, and cannot be conducted in real time. Therefore, we propose a digital system for the classification of epileptic EEG in real time on a Field Programmable Gate Array (FPGA). The implemented digital system comprised a communication interface, feature extraction, and classifier model functions. The Hjorth descriptor method was used for feature extraction of activity, mobility, and complexity, with KNN was utilized as a predictor in the classification stage. The proposed system, run on a The Zynq-7000 FPGA device, can generate up to 90.74% accuracy in normal, inter-ictal, and ictal EEG classifications. FPGA devices provided classification results within 0.015 s. The total memory LUT resource used was less than 10%. This system is expected to tackle problems in visual inspection and computer processing to help detect epileptic EEG using low-cost resources while retaining high performance and real-time implementation.

A field programmable gate array-based timing and control system for the dynamic compression sector.

A field programmable gate array (FPGA)-based timing and trigger control system has been developed for the Dynamic Compression Sector (DCS) user facility located at the Advanced Photon Source (APS) at Argonne National Laboratory. The DCS is a first-of-its-kind capability dedicated to dynamic compression science. All components of the DCS laser shock station-x-ray choppers, single-shot shutter, internal laser triggers, and shot diagnostics-must be synchronized with respect to the arrival of x rays in the hutch. An FPGA synchronized to the APS storage ring radio frequency clock (352 MHz) generates trigger signals for each stage of the laser and x-ray shutter system with low jitter. The developed FPGA-based control system was the first system used to control the laser and the shutter system since its commissioning, and it has been developing since then to improve the timing jitter. The system is composed of a Zynq FPGA, a debug card, line drivers, and a power supply. The delay and offsets of the trigger signals can be adjusted by using a user-friendly graphical user interface with high precision. The details of the system architecture, timing requirements, firmware, and software implementation along with the performance evaluation are presented in this paper. The system offers low timing jitter (15.5 ps rms) with respect to the APS 352 MHz clock, suitable for the 100 ps (FWHM) x-ray bunch duration at the APS.

A field programmable gate array-based biomedical noise reduction framework using advanced trilateral filter

Filtering is one of the essential tools utilized to remove undesirable features in biomedical images. Most biomedical image denoising systems are used for clinical diagnosis. So, in this paper, we use the advanced trilateral filter in the field programmable gate array (FPGA) for removing noise in the biomedical image. Generally, the trilateral filter is used as an edge preserving smoothing filter. This advanced approach of trilateral filter gives the best noise diminution and enhances the image quality. This paper also proposes the hardware implementation of an efficient FPGA-based advanced trilateral filter on real time execution. In this manuscript, we intend to design and implement the FPGA architecture using an advanced trilateral filter. Biomedical images with different noises are used during implementation and compared with the existing bilateral and trilateral architecture to assess the proposed architecture performance. For evaluating the performance metrics of the proposed advanced trilateral filter on MATLAB platform, peak signal-to-noise ratio (PSNR), mean squared error (MSE) and structured similarity index (SSIM) are calculated for different biomedical images – such as brain (MRI), chest (x-ray) and lungs (CT) – with different noises – such as salt and pepper, Gaussian, Poisson and Speckle noises – compared with existing bilateral filter and trilateral filter, respectively. The proposed advanced trilateral filter implementations are checked on Virtex-6, Virtex-7 and Zynq FPGA development board using Verilog programming language in Xilinx ISE 14.5 design tools. The simulation outcomes display that the FPGA execution of the advanced trilateral filter contains better noise removal efficiency in biomedical images compared with the existing bilateral and trilateral filter.

Detection of brain stroke in the MRI image using FPGA

One of the most important difficulties which doctors face in diagnosing is the analysis and diagnosis of brain stroke in magnetic resonance imaging (MRI) images. Brain stroke is the interruption of blood flow to parts of the brain that causes cell death. To make the diagnosis easier for doctors, many researchers have treated MRI images with some filters by using Matlab program to improve the images and make them more obvious to facilitate diagnosis by doctors. This paper introduces a digital system using hardware concepts to clarify the brain stroke in MRI image. Field programmable gate arrays (FPGA) is used to implement the system which is divided into four phases: preprocessing, adjust image, median filter, and morphological filters alternately. The entire system has been implemented based on Zynq FPGA evaluation board. The design has been tested on two MRI images and the results are compared with the Matlab to determine the efficiency of the proposed system. The proposed hardware system has achieved an overall good accuracy compared to Matlab where it ranged between 90.00% and 99.48%.

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power‐efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power‐efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface

As computational and functional brain model development are solely dependent upon the data acquired from the neural interface, this device plays a vital role in both prosthetic developments and neurological experiments. A wireless neural interface is preferred over a traditional wired one because it can maximize the comfort of the subject and ensure the freedom of movement while implemented. This paper describes the field programmable gate array (FPGA) prototype design of a low-power multichannel neuron activity extraction unit suitable for a wireless neural interface. To achieve the low-power requirement, we proposed a novel neural signal extraction algorithm which can provide an up to 6000X transmission rate reduction considering the input signal. Consequently, this technique offers at least 2X power reduction compared to the state-of-the-art systems. We implemented this scheme in Xilinx Zynq-7000 FPGA, which can be used as an intermediate transition towards the application specific integrated circuit (ASIC) design for on-chip neural signal processing. The proposed FPGA prototype offers reconfigurable computability, which means the model can be modified and verified according to prerequisites before the final ASIC design. This prototype consists of a signal filtering unit and a signal extraction unit which can be used either as stand-alone units or combined as a complete system. Our proposed scheme also provides a provision to work as a single-channel or a scalable multichannel interface based on user’s demands. We collected practical neural signals from rat brains and validated the efficacy of the implemented system using in-silico signal processing.

Single Event Effects Characterization of the Programmable Logic of Xilinx Zynq-7000 FPGA Using Very/Ultra High-Energy Heavy Ions

This article studies the impact of radiation-induced single-event effects (SEEs) in the Zynq-7000 field programmable gate array (FPGA) and presents an in-depth analysis of the SEE susceptibility of all the memories of the programmable logic. The radiation experiments were performed in the CERN North Area facility and in the GSI Helmholtz Centre for Heavy Ion Research using very/ultra high-energy heavy ions. The offline analysis of the radiation experimental results produced a deep understanding for various SEE phenomena observed in the Zynq-7000 FPGAs, such as single-event function interrupts (SEFIs), single-event transient (SET) in global signals, and multiple bit upsets that could be key issues for the design of an effective SEE mitigation approach.

A Reconfigurable Random Number Generator Based on the Transient Effects of Ring Oscillators

This brief presents a reconfigurable Random Number Generator (RNG) based on transient effect of ring oscillators. Users can select a method based on the irregular sampling of a regular waveform or on the regular sampling of an irregular waveform to obtain a random bit sequence to be used in different applications, such as lightweight cryptography or high-security communication. The entropy is acquired by exploiting Transient Effect Ring Oscillators (TEROs). The proposed fully-digital RNG structure is firstly implemented on a Zynq-7000 FPGA (Field Programmable Gate Array) without any post-processing method such as the Von Neumann. In addition to the RNG structure, an on-the-line test module based on FIPS 140–2 is also implemented to check the randomness of the produced data statistically in real time. Users can change the statistical test parameters according to their desired security levels. Finally, an ASIC (Application Specific Integrated Circuits) implementation of the proposed RNG is done following the Cadence digital design flow for the TSMC 180 nm CMOS process. The implemented ASIC design occupies an area of 0.85 mm x 0.85 mm and the estimated power required is 11.827 mW.

Enabling heterogeneous ray‐tracing acceleration in edge/cloud architectures

SummaryThe ray‐tracing algorithm is very costly regarding time complexity and while many techniques have been conceived over the years with the purpose of accelerating its execution, one stands out: parallelism exploitation of ray‐triangle intersection operations. In this sense, field‐programmable gate arrays (FPGAs) have plenty resources to run specialized accelerators that execute multiple operations in parallel. Moreover, modern FPGAs are embedded with multiprocessor systems‐on‐chip based on ARM architecture, which can be used simultaneously with the FPGA programmable logic to further accelerate the application execution. In this work, we present and analyze a reconfigurable accelerator for ray‐tracing specialized in computing ray‐triangle intersections at the network edge of a heterogeneous cloud computing environment. The accelerator is specified using Xilinx high‐level synthesis and is implemented in a Xilinx Zynq FPGA (XC7Z020‐1CLG400C). We also present an execution model which enables the exploitation of the available computing elements of the heterogeneous system: ARM Cortex‐A53, FPGA programmable logic, and cloud machines. Experimental performance and synthesis results show that the heterogeneous system can efficiently render a simplified version of the Stanford Bunny model when using the hardware accelerator with up to six instances of a ray‐triangle intersection unit together with the other computing resources.

Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

PurposeSynthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor.Design/methodology/approachA chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library.FindingsThe heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization.Originality/valueVery few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.

Design and Implementation of Robust Low Power ECG Pre-processing Module

A robust low power Electrocardiogram (ECG) pre-processor is proposed to extract the useful information from biomedical signal. The methodology uses window-based efficient design that consumes less power and resources of Field Programmable Gate Array (FPGA). The comparison has been done among different window functions and filter architectures (Symmetric and Anti-symmetric). The entire hardware implementation is carried out on ZedBoard Zynq-7000 FPGA board. The inference has been drawn that symmetric Bartlett window consumes only 0.88%, 5.13%, and 9% of LUTs, slice registers and DSPs units respectively. 35mW of dynamic and 105 mW of static power is consumed by the pre-processor module. The proposed design is recommended to find applications in wearable and portable biomedical equipments.

Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.