Zynq-7000 Field Programmable Gate Array Research Articles

Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this article has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation. On the other hand, it describes the implementation of a robotic arm controller based on the DLS to numerically solve Inverse Kinematics problems over a heterogeneous FPGA. Assessments involve a Trossen Robotics WidowX robotic arm controlled by a Digilent ZedBoard provided with a Xilinx Zynq FPGA that computes the Inverse Kinematic.

FPGA-Accelerated Hash Join Operation for Relational Databases

Equi-join operations are fundamental in database management. Hash join algorithms are often used to reduce the computational complexity of join operations; however, their performance is influenced by imperfect data distributions caused by hash collisions. To resolve these collisions, this brief designs a hardware-accelerated hash join architecture. This architecture aims to break the trade-off between complex hash functions, which is computationally expensive, and hash join performance. First, two hash functions are employed to distribute data as evenly as possible, and then multiple entries of the collision list are provided; finally, a small number of the static random-access memory (SRAM) of the field-programmable gate arrays (FPGAs) are used to conduct the join operation in parallel. The proposed method yields high-throughput and is resource-efficient, as it does not require reprocessing of data; further, it improves hash table utilization. The results of implementing this architecture on a Xilinx Zynq FPGA platform indicate an accelerated throughput that is a minimum of 4.2× that of previous hardware-accelerated hash join methods.

Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash)

Electronic money (e-money or e-Cash) is the digital representation of physical banknotes augmented by added use cases of online and remote payments. This paper presents a novel, anonymous e-money transaction protocol, built based on physical unclonable functions (PUFs), titled PUF-Cash. PUF-Cash preserves user anonymity while enabling both offline and online transaction capability. The PUF’s privacy-preserving property is leveraged to create blinded tokens for transaction anonymity while its hardware-based challenge–response pair authentication scheme provides a secure solution that is impervious to typical protocol attacks. The scheme is inspired from Chaum’s Digicash work in the 1980s and subsequent improvements. Unlike Chaum’s scheme, which relies on Rivest, Shamir and Adlemans’s (RSA’s) multiplicative homomorphic property to provide anonymity, the anonymity scheme proposed in this paper leverages the random and unique statistical properties of synthesized integrated circuits. PUF-Cash is implemented and demonstrated using a set of Xilinx Zynq Field Programmable Gate Arrays (FPGAs). Experimental results suggest that the hardware footprint of the solution is small, and the transaction rate is suitable for large-scale applications. An in-depth security analysis suggests that the solution possesses excellent statistical qualities in the generated authentication and encryption keys, and it is robust against a variety of attack vectors including model-building, impersonation, and side-channel variants.

An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis.

Connected Component Analysis (CCA) plays an important role in several image analysis and pattern recognition algorithms. Being one of the most time-consuming tasks in such applications, specific hardware accelerator for the CCA are highly desirable. As its main characteristic, the design of such an accelerator must be able to complete a run-time process of the input image frame without suspending the input streaming data-flow, by using a reasonable amount of hardware resources. This paper presents a new approach that allows virtually any feature of interest to be extracted in a single-pass from the input image frames. The proposed method has been validated by a proper system hardware implemented in a complete heterogeneous design, within a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) System on Chip (SoC) device. For processing 640 × 480 input image resolution, only 760 LUTs and 787 FFs were required. Moreover, a frame-rate of ~325 fps and a throughput of 95.37 Mp/s were achieved. When compared to several recent competitors, the proposed design exhibits the most favorable performance-resources trade-off.

An FPGA implementation of the matching pursuit algorithm for a compressed sensing enabled e-Health monitoring platform

Wireless monitoring of physiological signals is an evolving direction in personalized medicine and home-based e-Health systems. There are several constraints in designing such systems, with two of the most important being energy consumption and data compression. Compressed Sensing (CS) is an emerging data compression technique that can be used to overcome those constraints. This work presents a low-complexity CS hardware implementation on a Field-Programmable Gate Array (FPGA) for the reconstruction of compressively sensed signals using the matching pursuit (MP) algorithm, targeting health-care applications. The proposed hardware design is based on pipeline optimization of the Programmable Logic (PL) implementation performed on the Zynq FPGA, which provides a significant performance enhancement, namely an increased processing speed and a reduced computational time since it is 115x faster than the Matlab implementation and 75x faster than the Processing System (PS) implementation carried out on the same Zynq FPGA device, while achieving alternative a high-quality signal recovery with a Peak Signal to Noise Ratio (PSNR) of 23.8 dB. Comparisons against other state-of-the-art methods showed that the low complexity of the MP algorithm can be exploited for providing almost similar results to more complex algorithms using 87–583 less Digital Signal Processor (DSP) cores, 28–540 less Block RAMs and 10,300 to 84,700 less Look-Up Table (LUT) slices.

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators

Air traffic has seen tremendous growth over the past decade pushing the need for enhanced air traffic management schemes. The $L$ -band digital aeronautical communication system (LDACS) is gaining traction as a scheme of choice, and aims to exploit the capabilities of modern digital communication techniques and computing architectures. Cognitive radio-based approaches have also been proposed for LDACS to improve spectrum efficiency and communication capacity; however, these require intelligent compute capability in aircrafts that enforce limited space and power budgets. This paper proposes the use of multiplierless correlation to enable spectrum sensing in LDACS air-to-ground links, and its integration into the on-board LDACS system. The proposed architecture offers improved performance over traditional energy detection (ED) even at low signal-to-noise ratio (SNR) with lower energy consumption than a multiplier-based correlator, while also assisting in receiver synchronization. We evaluate the proposed architecture on a Xilinx Zynq field-programmable gate array and show that our approach results in 28.3% reduction in energy consumption over the multiplier-based approach. Our results also show that the proposed architecture offers 100% accuracy in detection even at −12-dB SNR without requiring additional circuitry for noise estimation, which are an integral part of ED-based approaches.

A Bias-Bounded Digital True Random Number Generator Architecture

Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values.

The Design of Sobel Edge Extraction System on FPGA

Edge is a basic feature of an image, the purpose of edge detection is to reduce the amount of data in an image while preserving the shape information of objects .Field programmable gate arrays (FPGA) are best suited to implement image processing algorithms with the reason that it provides infinite reprogram ability and high parallelism.The aim of this paper is to design a real-time sobel extract system based on HLS method and the implement it on ZYNQ FPGA. The result shows the software processing time is almost 80 times than the hardware processing. The hardware acceleration has remarkable effect on sobel filtering.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9ps time-interval RMS precision, 16 TDC channels with 6.9ps RMS precision, or 8 TDC channels with 5.8ps RMS precision. All TDCs have a 380M Samples/second measurement throughput and a 2.63ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Performance Analysis of Micro blaze Implemented GPS-INS Integrated Systems on Spartan 6 and Zynq FPGAs

This paper compares the performances of two loosely coupled Micro blaze Implemented GPS-INS Integrated Systems On Spartan 6 And Zynq FPGAs. The first system usesa Micro blaze implemented GPS-INS integrated system on Spartan 6 Field Programmable Gate Array (FPGA) for inertial navigation solution and Kalman filter computation.The second system uses a Micro blaze implemented GPS-INS integrated system on Zynq FPGA for inertial navigation solution and Kalman filter computation . Real time issues related to accuracy of position, GPS outages, Selective availability of GPS, Higher variances of accelerometers, Resource usage of FPGA in terms of Slices, DSP48 and Block Random Access Memory (BRAM), Computation time, latency, and power consumption are presented.The systems are designed to give real time processed navigation solutions with an update rate of 100 Hz.