ZnO Transistors Research Articles

Solution-based surface modification method for high-performance ZnO transistors

A solution-based surface modification method is first proposed for improving electrical performance of the ZnO transistors. The ZnO transistors are infiltrated for treatment in the 0.01 mol/L NH4Cl solution, and the effects of treatment time on electrical properties are examined. We find that turn-on voltage (VON) positively correlates with the treatment time, consequently sub-threshold swing (SS) is optimized significantly. After treatment for 30 s, the device showed a shift of VON from −1.96 V to −1.24 V. Additionally, the SS decreased from 154.5 mV/dec to 104.4 mV/dec, and the μFE increased from 20.69 cm2/V·s to 25.55 cm2/V·s. The XPS results imply that the surface modification method effectively reduces oxygen vacancies of the ZnO active layer, which achieves the target of adjusting VON and SS. Besides, characterization results show that the surface is smoother and the wettability is enhanced after treatment. This solution-modified strategy is expected to be put into practical application due to the advantages of easy operation, low cost, low-temperature environmental protection, and capable of large-scale treatment.

Study of Vertical Phototransistors Based on Integration of Inorganic Transistors and Organic Photodiodes.

We investigate the inorganic/organic hybrid vertical phototransistor (VPT) by integrating an atomic layer deposition-processed ZnO (ALD-ZnO) transistor with a prototype poly(3-hexylthiophene):[6,6]-phenyl-C61-butyric acid methyl ester (P3HT:PC61BM) blend organic photodiode (OPD) based on an encapsulated source electrode geometry, and discuss the device mechanism. Our preliminary studies on reference P3HT:PC61BM OPDs show non-ohmic electron injection between the ALD-ZnO and P3HT:PC61BM layers. However, the ALD-ZnO layer enables the accumulation of photogenerated holes under negative bias, which facilitates electron injection upon illumination and thereby enhances the external quantum efficiency (EQE). This mechanism underpins the photoresponse in the VPT. Furthermore, we demonstrate that the gate field in the VPT effectively modulates electron injection from the ALD-ZnO layer to the top OPD, resulting in the VPT operating as a non-ohmic OPD in the OFF state and as an ohmic OPD in the ON state. Benefiting from the unique transistor geometry and gate modulation capability, this hybrid VPT can achieve an EQE of 45,917%, a responsivity of 197 A/W, and a specific detectivity of 3.4 × 1012 Jones under 532 nm illumination and low drain-source voltage (Vds = 3 V) conditions. This transistor geometry also facilitates integration with various OPDs and the miniaturization of the ZnO channel area, offering an ideal basis for the development of highly efficient VPTs and high-resolution image sensors.

Investigation of width-to-length ratio on the performance of ZnO transistors and inverters

Abstract Oxide transistors have attracted considerable attention in the field of integrated circuits. In this work, ZnO transistors were fabricated using atomic layer deposition process, with various width-to-length (W/L) ratios of 100/10 μm, 50/10 μm, 20/5 μm, 10/5 μm, and 10/10 μm. Among them, the ZnO transistor with a W/L ratio of 10/10 μm demonstrated superior electrical performance, including a field-effect mobility of 37.65 cm²V-1s-1, a subthreshold swing of 112.50 mV/decade, and a turn-on voltage of -0.50 V. Additionally, n-type ZnO transistors were used to design inverter circuits, where the voltage gain was found to be inversely correlated with the W/L ratio of the load transistor. A maximum voltage gain of 59.33 V/V was achieved at a supply voltage of 5 V using a load transistor with a W/L ratio of 10/5 μm. These results indicate that ZnO transistors, with optimized design, offer promising performance for future integrated circuit applications.

The Extraction of the Density of States of Atomic-Layer-Deposited ZnO Transistors by Analyzing Gate-Dependent Field-Effect Mobility

In this study, we investigated the density of states extraction method for atomic-deposited ZnO thin-film transistors (TFTs) by analyzing gate-dependent field-effect mobility. The atomic layer deposition (ALD) method offers ultra-thin and smooth ZnO films, but these films suffer from interface and semiconductor defects, which lead to disordered localized electronic structures. Hence, to investigate the unstable localized structure of ZnO TFTs, we tried to derive the electronic state relationship by assuming field-effect mobility can be expressed as a gate-dependent Arrhenius relation, and the activation energy in the relation is the required energy for hopping. Following this derived relationship, the DOS of the atomic-deposited ZnO transistor was extracted and found to be consistent with those using temperature-dependent measurements. Moreover, to ensure the proposed method is reliable, we applied methods for the extraction of DOSs of doped ZnO transistors, which show enhanced mobilities with shifted threshold voltages, and the results show that the extraction method is reliable. Thus, we can state that the mobility-based DOS extraction method offers practical benefits for estimating the density of states of disordered transistors using a single transfer characteristic of these devices.

High-Performance Vertical Light-Emitting Transistors Based on ZnO Transistor/Quantum-Dot Light-Emitting Diode Integration and Electron Injection Layer Modification.

Vertical light-emitting transistors (VLETs) consisting of vertically stacked unipolar transistors and organic light-emitting diodes (OLEDs) have been proposed as a prospective building block for display technologies. In addition to OLEDs, quantum-dot (QD) LEDs (QLEDs) with high brightness and high color purity have also become attractive light-emitting devices for display applications. However, few studies have attempted to integrate QLEDs into VLETs, as this not only involves technical issues such as compatible solution process of QDs and fine patterning of electrodes in multilayer stacked geometries but also requires a high driving current that is demanding on transistor design. Here we show that these integration issues of QLEDs can be addressed by using inorganic transistors with robust processability and high mobility, such as the studied ZnO transistor, which facilitates simple fabrication of QD VLETs (QVLETs) with efficient emission in the patterned channel area, suitable for high-resolution display applications. We perform a detailed optimization of QVLET by modifying ZnO:polyethylenimine nanocomposite as the electron injection layer (EIL) between the integrated ZnO transistor/QLED, and achieve the highest external quantum efficiency of ~3% and uniform emission in the patterned transistor channel. Furthermore, combined with a systematic study of corresponding QLEDs, electron-only diodes, and electroluminescence images, we provide a deeper understanding of the effect of EIL modification on current balance and distribution, and thus on QVLET performance.

Hf-doped ZnO transistor with high bias stability and high field-effect mobility by modulation of oxygen vacancies and interfaces

ZnO-based thin film transistors (TFTs) with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density. In this work, we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment. The results show that the cycle ratio of Zn/Hf is optimized to be 10:1, and the corresponding atomic ratio is 2.24%. The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases, owning to the decrease of the oxygen vacancies and interface trap density. Furthermore, we developed Hf-doped ZnO TFT with high bias stability by introducing HfO2 intermediate layer between the active layer and SiO2 dielectric layer, and the shift of threshold voltage is as low as -0.273 V, showing high bias stability. Also, the device has the high field-effective mobility of 52.4 cm2/Vs, low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6 × 108. The results indicate a promising fabrication method for high-performance ZnO-based TFTs, which may be applied in logic circuits, radio frequency identification and so on.

Ultrastrong coupling in Super Yellow polymer microcavities and development of highly efficient polariton light-emitting diodes and light-emitting transistors.

We present detailed studies on exciton-photon coupling and polariton emission based on a poly(1,4-phenylenevinylene) copolymer, Super Yellow (SY), in a series of optical microcavities and optoelectronic devices, including light-emitting diode (LED) and light-emitting transistor (LET). We show that sufficiently thick SY microcavities can generate ultrastrong coupling with Rabi splitting energies exceeding 1 eV and exhibit spectrally narrow, nearly angle-independent photoluminescence following lower polariton (LP) mode dispersion. When the microcavity is designed with matched LP low-energy state and exciton emission peak for radiative pumping, the conversion efficiency from exciton to polariton emission can reach up to 80%. By introducing appropriate injection layers in a SY microcavity and optimizing the cavity design, we further demonstrate a high-performance ultrastrongly coupled SY LED with weakly dispersive electroluminescence along LP mode and a maximum external quantum efficiency (EQE) of 2.8%. Finally, we realize an ultrastrongly coupled LET based on vertical integration of a high-mobility ZnO transistor and a SY LED in a microcavity, which enables a large switching ratio, uniform emission in the ZnO pattern, and LP mode emission with a maximum EQE of 2.4%. This vertical LET addresses the difficulties of achieving high emission performance and precisely defining the emission area in typical planar LETs, and opens up the possibility of applying various strongly coupled emitters for advanced polariton devices and high-resolution applications.

High Efficiency and Uniform Emission in Micropixelated Inorganic/Organic Hybrid Vertical Light-Emitting Transistors and Displays

Vertical light-emitting transistors (VLETs) fabricated by integrating organic vertical transistors and organic light-emitting diodes (OLEDs) have been proposed as a prospective building block for display technologies. However, organic vertical transistors normally have non-ohmic injection and a low-mobility channel, resulting in low VLET performance compared to the pristine OLED. The difficulty of fine patterning the source electrode and organic layer in a stacked VLET geometry has also been a technical issue limiting industrial applications. This paper reports on a simple approach to realize a high-performance, miniaturized VLET by using a highly conductive, well-designed inorganic transistor. Here, we investigate the ZnO transistor configured with an insulator-encapsulated source electrode to confine the current pathway in the VLET, which can be easily fabricated and integrated with various solution-processed or vacuum-sublimed inverted OLEDs (IOLEDs). This ZnO transistor exhibits ohmic contact and a high electron mobility of >10 cm2/(V s) that enables effective electron injection and lateral transport in the VLET, forming a millimeter-scale density gradient (channel depth) for strong surface emission. Furthermore, the high mobility of ZnO facilitates the design of a simple source pattern with a large aperture ratio on the ZnO area to control the current density and distribution and thus the VLET output. From a systematic study of the source design, we show that the ZnO transistor can be optimized to achieve homogeneously high conductivity in the ON state and yield the best VLET performance with maximum emission intensity and efficiency close to those of the IOLED, while the emission can be spatially uniform and precisely defined by the ZnO pattern. Finally, we implement a micropixelated VLET-based active matrix panel to demonstrate the prospect of high-resolution display applications.

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional (3D) vertical architecture transistors represent an important technological pursuit, which have distinct advantages in device integration density, operation speed, and power consumption. However, the fabrication processes of such 3D devices are complex, especially in the interconnection of electrodes. In this paper, we present a novel method which combines suspended electrodes and focused ion beam (FIB) technology to greatly simplify the electrodes interconnection in 3D devices. Based on this method, we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al2O3 gate-oxide both grown by atomic layer deposition. Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires, which avoid cumbersome steps in the traditional 3D structure fabrication technology. Both single pillar and arrays devices show well behaved transfer characteristics with an I on/I off current ratio greater than 106 and a low threshold voltage around 0 V. The ON-current of the 2 × 2 pillars vertical channel transistor was 1.2 μA at the gate voltage of 3 V and drain voltage of 2 V, which can be also improved by increasing the number of pillars. Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.

Complementary Hybrid Semiconducting Superlattices with Multiple Channels and Mutual Stabilization.

An organic-inorganic hybrid superlattice with near perfect synergistic integration of organic and inorganic constituents was developed to produce properties vastly superior to those of either moiety alone. The complementary hybrid superlattice is composed of multiple quantum wells of 4-mercaptophenol organic monolayers and amorphous ZnO nanolayers. Within the superlattice, multichannel formation was demonstrated at the organic-inorganic interfaces to produce an excellent-performance field effect transistor exhibiting outstanding field-effect mobility with band-like transport and steep subthreshold swing. Furthermore, mutual stabilizations between organic monolayers and ZnO effectively reduced the performance degradation notorious in exclusively organic and ZnO transistors.

Printed Water-Based ITO Nanoparticle via Electrohydrodynamic (EHD) Jet Printing and Its Application of ZnO Transistors

An electrohydrodynamic jet (EHD) printing process was optimized for the patterning of an indium tin oxide (ITO) nanoparticles ink by manipulating its surface tension through the addition of a nonionic surfactant, Triton X-100 (TX-100). As a result, a stable cone-jet mode was performed, which could provide printed drops with the smallest diameter and printing fidelity among EHD jet printing modes, and lead to a line width ranging from 230 µm to 30 µm in addition to well-define patterns with various shapes for ITO transparent conducting electrodes (TCEs). The multi-printing technique and subsequent thermal annealing for printed ITO TCEs allows improvement in its electrical conductivity. In addition, the evolution of the chemical composition and crystalline structure of the printed ITO TCE according to the annealing temperature was investigated to determine the optimal conditions to utilize printed ITO nanoparticles for ZnO-based thin-film transistors.

Relatively Low-Temperature Processing and Its Impact on Device Performance and Reliability

Fabrication of MoS2, ZnO, and IGZO transistors at low enough temperatures that are suitable for large-area/flexible electronics is presented. Evaluating critical processing conditions and approaches on device performance is critical to understanding and improving devices to enable large-area/flexible circuits for the IoT. For MoS2, a study of the implications of photoresist residue on MoS2 in the source/drain contact region was done. Results determined that an O2 plasma exposure in this location can remove the resist residue and create a robust TiOx/MoS2 contact, where an ~15x increase in mobility and ~20x reduction in contact resistance was achieved for O2 plasma treated transistors. Thin-film transistor fabrication of ZnO and IGZO as the semiconductor yielded saturation mobilities of 14.2 and 9.0 cm2/V•s, respectively. Among other parameters, the contact resistance was noticeably lower for ZnO due to its polycrystalline morphology compared to the amorphous IGZO, which was determined to be more resistive.

High carrier mobility low-voltage ZnO thin film transistors fabricated at a low temperature via solution processing

Wide-bandgap ZnO TFTs have many potential applications in large-area, flexible electronics and transparent devices because of their low cost, high performance and excellent optical transmittance. High-performance ZnO TFTs fabricated via simple solution processing have been widely studied. However, the key issues of solution-processable ZnO TFTs are the relatively high processing temperature (> 300 °C) and the high operating voltage for achieving the desired electrical properties. Here, we successfully fabricated low-voltage ZnO TFTs at an annealing temperature of ≤ 250 °C. The resulting ZnO transistors with high-k terpolymer P(VDF-TrFE-CFE) showed a mobility of up to 5.3 cm2 V−1 s−1 and an on/off ratio of > 105 at 3 V. Furthermore, the influence of the dielectric constant on the carrier mobility was investigated. A lower k-value dielectric resulted in a high carrier mobility under the same carrier density. Therefore, with a low-k CYTOP dielectric applied to modify the interface between the ZnO semiconductor and the P(VDF-TrFE-CFE) layer, ZnO transistors annealed at 250 °C showed an electron mobility of 13.6 cm2 V−1 s−1 and an on/off ratio of > 105 at 3 V. To the best of our knowledge, this mobility is the highest value reported to date among the low-voltage solution-processable undoped ZnO TFTs annealed at temperatures of ≤ 300 °C.

Study of device instability of bottom-gate ZnO transistors with sol–gel derived channel layers

In this paper, the authors report the device instability of solution based ZnO thin film transistors by studying the time-evolution of electrical characteristics during electrical stressing and subsequent relaxation. A systematic comparison between ambient and vacuum conditions was carried out to investigate the effect of adsorption of oxygen and water molecules, which leads to the creation of defects in the channel layer. The observed subthreshold swing and change in field effect mobility under gate bias stressing have supported the fact that oxygen and moisture directly affect the threshold voltage shift. The authors have presented the comprehensive analysis of device relaxation under both ambient and vacuum conditions to further confirm the defect creation and charge trapping/detrapping process since it has not been reported before. It was hypothesized that chemisorbed molecules form acceptorlike traps and can diffuse into the ZnO thin film through the void on the grain boundary, being relocated even near the semiconductor/dielectric interface. The stretched exponential and power law model fitting reinforce the conclusion of defect creation by oxygen and moisture adsorption on the active layer.

Al‐Doped ZnO Transistors Processed from Solution at 120 °C

A simple Al‐doping method that is used to significantly enhance the operating characteristics of ZnO thin‐film transistors processed from solution at temperatures down to 120 °C is reported. The two‐step doping process relies on the dissolution of zinc oxide hydrate in ammonia hydroxide to form an aqueous Zn‐ammine complex solution and the subsequent immersion of Al pellets into it at room temperature. The pellets are then removed, and the doped precursor solution is spin‐coated onto the substrate followed by thermal annealing in air to form the n‐doped ZnO:Al layers. By controlling the immersion time of the Al pellets in the precursor solution, the free electron concentration in ZnO can be tuned. The resulting ZnO:Al layers are shown to be polycrystalline with tuneable electrical properties. ZnO:Al‐based transistors processed at 180 °C exhibit enhanced electron mobility when compared to intrinsic ZnO devices with the maximum values exceeding 5 cm2 V−1 s−1. Even when the process temperature is reduced to 120 °C, the ZnO:Al transistors retain their excellent operating characteristics with a maximum electron mobility of 3 cm2 V−1 s−1. This is amongst the highest values reported to date for soluton‐deposited ZnO transistors processed at 120 °C in air.

Hybrid Modulation-Doping of Solution-Processed Ultrathin Layers of ZnO Using Molecular Dopants.

An alternative doping approach that exploits the use of organic donor/acceptor molecules for the effective tuning of the free electron concentration in quasi-2D ZnO transistor channel layers is reported. The method relies on the deposition of molecular dopants/formulations directly onto the ultrathin ZnO channels. Through careful choice of materials combinations, electron transfer from the dopant molecule to ZnO and vice versa is demonstrated.

Memristive behavior in a junctionless flash memory cell

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, Al2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, Roff/Ron ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

Solution-processed SiO2 gate insulator formed at low temperature for zinc oxide thin-film transistors

A ZnO transistor with carrier mobility of 3 cm2 V−1 s−1 using a SiO2 insulator formed at low-temperature (180 °C) from solution-processed perhydropolysilazane.

Effects of hydrogen plasma treatment on the electrical behavior of solution-processed ZnO transistors

The effects of hydrogen plasma treatment on the active layer of top-contact zinc oxide thin film transistors are reported. The transfer characteristics of the reference devices exhibited large hysteresis effects and an increasing positive threshold voltage (VTH) shift on repeated measurements. In contrast, following the plasma processing, the corresponding characteristics of the transistors exhibited negligible hysteresis and a very small VTH shift; the devices also possessed higher field effect carrier mobility values. These results were attributed to the presence of functional groups in the vicinity of the semiconductor/gate insulator interface, which prevents the formation of an effective channel.

Design Considerations for ZnO Transistors Made Using Spatial ALD

We have used spatial atomic layer deposition (SALD) to fabricate metal oxide thin-film devices with unusually simple processes. Selective area deposition allows us to fabricate transistors and circuits additively and with digital design variations when used in combination with an inkjet-printed inhibitor. In a second approach, we use the conformal nature of SALD films to produce self-aligned sub-micron channel length vertical transistors that have large alignment tolerances and are suitable for high-performance thin-film electronics. We discuss device design considerations for both architectures.