ZnO Thin-film Transistors Research Articles

Saturation Mobility of 100 cm2 V-1 s-1 in ZnO Thin-Film Transistors through Quantum Confinement by a Nanoscale In2O3 Interlayer Using Spray Pyrolysis.

In this study, we present a comprehensive study on the fabrication and characterization of heterojunction In2O3/ZnO thin-film transistors (TFTs) aimed at exploiting the quantum confinement effect to enhance device performance. By systematically optimizing the thickness of the crystalline In2O3 (c-In2O3) layer to create a narrow quantum well, we observed a significant increase in saturation mobility (μSAT) from 12.76 to 97.37 cm2 V-1 s-1. This enhancement, attributed to quantum confinement, was achieved through the deposition of a 3 nm c-In2O3 semiconductor via spray pyrolysis. Various In2O3 layer thicknesses (2-5 nm) were obtained by adjusting precursor solution concentration, flow rate, and number of spray cycles. Post annealing treatments were employed to reduce the defects at the interface and within the oxide film, enhancing device stability and performance. Transmission electron microscopy (TEM) confirmed the uniformity of the c-In2O3 film thickness, while variations in thickness significantly influenced TFT performance, particularly the turn-on voltage (VGS) due to changes in the carrier concentration. Ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS) supported the formation of a potential well with a two-dimensional electron gas (2DEG). The study of single and multiple superlattice structures of consecutive c-In2O3 and c-ZnO layers provided insights into the effects of multiple quantum wells on the TFT performance. This research presents an advanced approach to TFT optimization, highlighting high reliability, and environmental and bias stabilities. These lead to enhanced mobility and performance uniformity through the precise control of c-In2O3 layer thickness for the quantum confinement effect.

The Extraction of the Density of States of Atomic-Layer-Deposited ZnO Transistors by Analyzing Gate-Dependent Field-Effect Mobility

In this study, we investigated the density of states extraction method for atomic-deposited ZnO thin-film transistors (TFTs) by analyzing gate-dependent field-effect mobility. The atomic layer deposition (ALD) method offers ultra-thin and smooth ZnO films, but these films suffer from interface and semiconductor defects, which lead to disordered localized electronic structures. Hence, to investigate the unstable localized structure of ZnO TFTs, we tried to derive the electronic state relationship by assuming field-effect mobility can be expressed as a gate-dependent Arrhenius relation, and the activation energy in the relation is the required energy for hopping. Following this derived relationship, the DOS of the atomic-deposited ZnO transistor was extracted and found to be consistent with those using temperature-dependent measurements. Moreover, to ensure the proposed method is reliable, we applied methods for the extraction of DOSs of doped ZnO transistors, which show enhanced mobilities with shifted threshold voltages, and the results show that the extraction method is reliable. Thus, we can state that the mobility-based DOS extraction method offers practical benefits for estimating the density of states of disordered transistors using a single transfer characteristic of these devices.

ZnO-based triboelectric nanogenerator and tribotronic transistor for tactile switch and displacement sensor applications

Tribotronics, the coupling of triboelectricity and semiconductors, is a novel field that has sparked much interest in the nanoelectronics and nanoenergy industries. This work presents the fabrication of a ZnO tribotronic transistor by combining a ZnO thin film transistor (ZnO-TFT) and a triboelectric nanogenerator (TENG) operating in vertical contact separation mode. A Si/SiO2/ZnO/Au structure was used to construct a bottom-gated ZnO-TFT. Radiofrequency (RF) magnetron sputtering was employed to deposit ZnO thin film, and the Au contact was achieved through thermal evaporation. A range of annealing temperatures was investigated, and ZnO TFT annealed at 500 °C exhibited a maximum electron mobility of 5.47 cm2/V s and a high on/off ratio of 105. We also investigated the photoresponse of this optimized ZnO-TFT using a UV LED. A vertical contact separation mode TENG was fabricated using ZnO (tribo-positive layer) and polyvinylidene difluoride (PVDF, tribo-negative layer) and combined with the ZnO TFT to fabricate a tribotronic transistor. The drain current of the tribotronic transistor dropped from 2.9 to 0.02 µA at a drain voltage of 5 V when the tribo layers were separated by 15 mm. Within the separation region of 2 mm, the device showed a 1.29 µA/mm change in drain current demonstrating its effectiveness in displacement sensing. Unlike conventional TFTs, the TENG's output could successfully control the tribotronic transistor's drain current and was innovative in such domains where conventional electrical components were constrained. Furthermore, this ZnO tribotronic device was used as an active smart tactile switch by simply touching or releasing the ZnO TENG with a finger.

Enlightenment of Deionized‐Water Bathing IGZO TFTs

AbstractAt present, amorphous indium–gallium–zinc oxide (IGZO) semiconductor has become the most commonly used semiconductor material and is widely used in flat panel displays and various sensors, but its performance is greatly affected by environmental factors, especially water. This study investigates the instability of IGZO thin‐film transistors (TFTs) soaked in deionized water. After 24 h bathing, the field‐effect mobility and threshold voltage change a little, but the subthreshold swing, positive bias stress and negative bias stress stability undergo clear degradation. Through comprehensive examination of the changes in the chemical composition, surface morphology and thickness of the IGZO films, it's found that IGZO experiences selective etching by deionized water, and consequently the film surface becomes rough and rich of In and oxygen vacancies, which can explain the variations on device performance well. In addition to the bathing experiment performed on In2O3, Ga2O3, and ZnO TFTs, a schematic image of the reaction between water and IGZO is depicted, showing the preferential loss of Ga and Zn located next to the oxygen vacancy.

22‐3: Negative Capacitance ZAO/ZnO Ferroelectric Thin‐Film Transistor for Neuromorphic Computing

We report complementary metal‐oxide semiconductor (CMOS)‐compatible, negative capacitance (NC) ferroelectric (FE) zirconium‐aluminum oxide (ZAO)/ZnO thin‐film transistors (TFTs) at a low thermal budget of 360 °C. The NC‐FE‐TFTs demonstrate uniform device‐to‐device performances, featuring a high memory window of 6.7 ± 0.1 V and steep subthreshold swing of 43 ± 4 mV dec–1 . The observation of negative differential resistance at room temperature confirms the NC effect in FE‐ZAO/ZnO TFTs. In addition, a learning accuracy of ≈92% is achieved, highlighting the potential for high precision neuromorphic computing application.

The stability analysis of In–Ga–ZnO thin film transistors with polyimide substrates based on Maxwell–Wagner effect

Flexible organic light-emitting diode display devices fabricated on polyimide (PI) substrates have more obvious residual image problems due to the abnormal threshold-voltage (Vth) shifts of a thin film transistor (TFT). In this paper, the Vth shift of TFT fabricated on a PI substrate was analyzed. We explained the worse bias stability and worse recovery of TFT with a PI substrate compared with TFT with a glass substrate, by an interlayer charging effect (Maxwell–Wagner effect) and a technology computer-aided design (Silvaco). When bias stress was applied for a long time, the interface between the PI substrate and the buffer layer will have a charging effect under the action of an electric field, and the charging charge will react on the channel and hinder the formation of the channel. We found that there are differences in the scale of charge under different voltage stress conditions, and this will result in different Vth shifts of driving TFTs for displays units.

Transistors with ferroelectric ZrXAl1−XOY crystallized by ZnO growth for multi-level memory and neuromorphic computing

Ferroelectric (FE) field-effect transistors are interesting for their non-destructive readout characteristic and energy efficiency but are difficult to integrate on silicon platforms. Here, FE ZrXAl1−XOY (ZAO) is demonstrated by compressive strain in contact with ZnO. The metal-ferroelectric-semiconductor-metal capacitor exhibits a substantial remnant polarization of 15.2 µC cm−2, along with a bowknot-like anti-clockwise hysteresis in the capacitance curves. The FE-ZAO gated ZnO thin-film transistor presents a large memory window (3.84 V), low subthreshold swing (55 mV dec−1), high ION/IOFF ratio (≈108), and low off-state current (≈1 pA). The grazing incidence X-ray diffraction and scanning transmission electron microscopy analyses reveal the ferroelectric rhombohedral phase (space group R3m) in the nanocrystal ZAO, containing an angle of ≈71.7° between the [111] and [11-1] directions with d111-spacing of 3.037 Å and d11-1-spacing of 2.927 Å. Finally, the memory and neuromorphic applications are analyzed by demonstrating multi-level memory and synaptic weight performance with a high learning accuracy of 91.82%.

Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals.

Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on-off ratio of 17.6 cm2V-1s-1, 0.71 V/dec, and 107, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications.

Transparent Structures for ZnO Thin Film Paper Transistors Fabricated by Pulsed Electron Beam Deposition.

Thin film transistors on paper are increasingly in demand for emerging applications, such as flexible displays and sensors for wearable and disposable devices, making paper a promising substrate for green electronics and the circular economy. ZnO self-assembled thin film transistors on a paper substrate, also using paper as a gate dielectric, were fabricated by pulsed electron beam deposition (PED) at room temperature. These self-assembled ZnO thin film transistor source-channel-drain structures were obtained in a single deposition process using 200 and 300 µm metal wires as obstacles in the path of the ablation plasma. These transistors exhibited a memory effect, with two distinct states, "on" and "off", and with a field-effect mobility of about 25 cm2/Vs in both states. For the "on" state, a threshold voltage (Vth on = -1.75 V) and subthreshold swing (S = 1.1 V/decade) were determined, while, in the "off" state, Vth off = +1.8 V and S = 1.34 V/decade were obtained. A 1.6 μA maximum drain current was obtained in the "off" state, and 11.5 μA was obtained in the "on" state of the transistor. Due to ZnO's non-toxicity, such self-assembled transistors are promising as components for flexible, disposable smart labels and other various green paper-based electronics.

Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric Thickness

Modulating Electrical Characteristics of ZnO Thin-Film Transistors by Scaling Down Gate Dielectric Thickness

Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors

AbstractThis paper presents a Computer‐aided design (CAD) model for a‐IGZO thin film transistors (TFTs) by adapting SPICE level‐61 RPI a‐Si: H (Hydrogenated Amorphous Silicon) TFT model and level‐62 RPI Poly‐Si (Poly Silicon) TFT model. This work provides a complete understanding of SPICE level‐61 and 62 model parameters, which must be tuned for a‐IGZO TFT simulation. The adapted SPICE models of level‐61 and level‐62 could model all regions of operation of the TFT, that is, above‐threshold and below‐threshold regions. Adapted RPI poly‐Si model also shows the kink effect in ZnO thin film transistors (TFTs) due to the recombination of electron–hole pairs in the channel via boundary trap states present in the poly‐Si TFTs thereby increasing the drain current in the transistors above pinch‐off region. The extracted performance parameters of the adapted models were found to be contiguous with experimental results. The maximum deviation in the subthreshold slope is approximately 5 mV/decade for level‐61 a‐Si TFT, and for level‐62 poly‐Si TFT, deviation in the subthreshold slope is even less, that is, 0.2 mV/decade. The experimental and simulated characteristics, extracted on‐to‐off ratio, negative bias reverse saturation current, and threshold voltage were almost similar. However, an average deviation of 2.4% and 2.27% was observed in the output characteristics of the adapted level‐61 and level‐62 models, respectively.

Improvement in the Stability of Cation (Si)/Anion (F or N) Codoped ZnO Thin-Film Transistors Formed via Atomic Layer Deposition

The characteristics of cation (Si) and anion (F or N) codoped ZnO thin films formed via atomic layer deposition and corresponding device properties were investigated for different anion doping concentrations with a fixed Si doping amount. All films exhibited the (100) primary diffraction peak, indicating a hexagonal wurtzite structure. All codoped ZnO films exhibited the same effect of oxygen vacancy passivation, i.e., reduced oxygen vacancy. However, the electrical and optical characteristics of the films exhibited contrasting tendencies depending on the type of anion element. The optimized device properties, i.e., the subthreshold swing, field-effect mobility, threshold voltage, and bias stability were 6.62 E − 01 V/dec, 5.10 cm2/V·s, -11.16 V, and 6.32 V in the Si/F-19 condition and 5.98 E − 01 V/dec, 16.60 cm2/V·s, 1.07 V, and 0.14 V in the Si/N-19 condition, respectively. These characteristics were attributable to the correlation effects of the reduced interfacial trap density from Si doping and oxygen vacancy passivation from anion doping. Notably, the behavior of each anion was different in terms of the charge carrier concentration. First-principles calculations based on the density functional theory using the Vienna ab initio simulation package (VASP) code were performed to obtain valuable insights into the energy band structure in terms of the performance of the codoped ZnO films.

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors.

This study presents the disorderedness effects on the subthreshold characteristics of atomically deposited ZnO thin-film transistors (TFTs). Bottom-gate ZnO TFTs show n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, degradable subthreshold swing. The charge-transport characteristics of the disordered semiconductor TFTs are severely affected by the localized trap states. Thus, we posit that the disorderedness factors, which are the interface trap capacitance and the diffusion coefficient of electrons, would result in the degradation. Considering the factors as gate-dependent power laws, we derive the subthreshold current-voltage relationship for disordered semiconductors. Notably, the gate-dependent disorderedness parameters are successfully deduced and consistent with those obtained by the gm/Ids method, which was for the FinFETs. In addition, temperature-dependent current-voltage analyses reveal that the gate-dependent interface traps limit the subthreshold conduction, leading to the diffusion current. Thus, we conclude that the disorderedness factors of the ZnO films lead to the indefinable subthreshold swing of the ZnO TFTs.

Fabrication and investigation of the electrical performance of nitrogenated bilayer ZnO:N/ZnO thin-film transistors

In this study, a bilayer ZnO:N/ZnO thin-film transistors (TFTs) was designed to improve both the performance and stability of single-layer ZnO TFTs, using the effects of N-treatment on oxygen vacancy (VO) and the interface trap density. Bilayer ZnO:N/ZnO films and related TFTs were fabricated via radiofrequency magnetron sputtering in a mixture of Ar and N2 gas at 150 °C. The electrical performance and bias-stress stability were systematically investigated. The bilayer ZnO:N/ZnO TFT exhibited a linear field-effect mobility of 13.6 cm2/Vs, high current on-to-off ratio (Ion/Ioff) of 1 × 107, small threshold voltage (Vth) of 2.6 V, and low subthreshold swing of 0.32 V/decade compared with single-layer undoped ZnO and ZnO:N TFTs. Moreover, ZnO:N/ZnO TFT exhibited small threshold voltage shifts (∆Vth) of 0.8 and –0.9 V according to positive bias illumination stress and negative bias illumination stress measurements, respectively. X-ray photoelectron spectroscopy analysis showed that the N-treatment passivated the VO defects, reduced the density of interface traps, and controlled the carrier concentration. Thus, the performance and stability of the ZnO:N/ZnO TFTs were improved. Therefore, ZnO:N/ZnO TFTs have good application prospects in transparent thin-film electronics and flat-panel displays.

Low temperature, highly stable ZnO thin-film transistors

A low-temperature and straightforward fabrication process for ZnO thin-film transistors (TFTs) with near-zero aging and negligible instability enabled by using an ultrathin oxide as a top-passivation layer is demonstrated. The process features bottom-gate top-contacts ZnO TFTs with ultrathin HfO2 or Al2O3 as passivation layers on top of the TFT followed by post-fabrication annealing (PFA). Devices with ultra-thin capping films of Al2O3 followed by a 150 °C PFA show threshold voltage shift (ΔVTH) of <1% after bias stress and negligible shift after aging. The devices show saturation threshold voltage (VTH-SAT) of 2.70 V, saturation mobilities larger than 10 cm2/V·s, and current ION/IOFF ratios >106. On the contrary, devices without nanofilm show similar performance to those with Al2O3 but show more considerable instability to aging and bias stress (ΔVTH > 5%). Also, devices with HfO2 as a capping layer shows severe instability (ΔVTH > 40%). A degradation mechanism to explain the improved aging and reliability performance is also discussed.

Hf-doped ZnO transistor with high bias stability and high field-effect mobility by modulation of oxygen vacancies and interfaces

ZnO-based thin film transistors (TFTs) with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density. In this work, we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment. The results show that the cycle ratio of Zn/Hf is optimized to be 10:1, and the corresponding atomic ratio is 2.24%. The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases, owning to the decrease of the oxygen vacancies and interface trap density. Furthermore, we developed Hf-doped ZnO TFT with high bias stability by introducing HfO2 intermediate layer between the active layer and SiO2 dielectric layer, and the shift of threshold voltage is as low as -0.273 V, showing high bias stability. Also, the device has the high field-effective mobility of 52.4 cm2/Vs, low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6 × 108. The results indicate a promising fabrication method for high-performance ZnO-based TFTs, which may be applied in logic circuits, radio frequency identification and so on.

Composition‐Dependent High‐Performance Phototransistors Based on Solution Processed CH3NH3PbI3/ZnO Heterostructures

AbstractRecently, hybrid organic−inorganic perovskites have emerged as promising photo‐sensing materials for next‐generation solution‐processed phototransistors, achieving high responsivity, detectivity, and fast response. Here, a phototransistor that can detect visible light using a low‐cost, solution processed methylammonium lead iodide/zinc oxide (CH3NH3PbI3/ZnO) heterostructure is reported. While typical ZnO thin‐film transistors (TFTs) do not show any photocurrent under visible light illumination, CH3NH3PbI3 (MAPbI3) coated ZnO TFTs exhibit substantial photocurrent. Additionally, the optical, morphological, and structural characteristics of the light‐absorbing layers are further controlled by altering the precursor ratio of methylammonium iodide and lead (II) iodide (MAI:PbI2), which in turn affects the photosensitivity. Stoichiometric composition (MAI:PbI2 = 1:1) of MAPbI3 demonstrates optimal characteristics with a responsivity of 234 A/W and a high detectivity of 3.74 × 1013 Jones under white light illumination. The high photo‐responsivity and detectivity result from the combination of the suitable optoelectronic properties of the stoichiometric MAPbI3 film and its smooth interface with the ZnO channel.

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.