Nonvolatile memories (NVMs) made of MOS capacitors with nanocrystals embedded high-k gate dielectrics have been reported [1-7]. Nanocrystals made of various types of materials, e.g., Si, ITO, ZnO, RuO, CdS, and CdSe, were used as the charge trapping media in the device [1,5]. Both holes and electrons can be stored in this kind of device. Depending on the band structure and charge affinity of the nanocrystal material, samples can preferentially trap one type of charges over the other type of charges. For example, the nc-ITO or nc-MoOx embedded samples prefer to trap holes [6]. On the other hand, the nc-RuO embedded sample prefers to trap electrons [7]. There are many methods in preparing the nanocrystals embedded dielectric structure. Previously, our group has used the in-situ crystallization method to prepare the sample, i.e., forming embedded nanocrystals by annealing a tri-layer thin layer structure. The originally continuous thin embedded layer was transformed into discrete nanocrystals after a high temperature treatment. However, if the annealing time is long, the thermal budget can be large, which affects the interface layer formation and the dopant distribution in the substrate. A low thermal budget pulsed rapid thermal annealing (PRTA) method has been used to transform the amorphous silicon into polycrystalline for the thin film transistor (TFT) and solar cell applications [8]. In this paper, the PRTA method is used to form nanocrystals embedded high-k dielectric for the nonvolatile memory application. The Zr-doped HfO2 (ZrHfO) high-k film is used as the dielectric for its excellent bulk and interface properties, e.g., higher crystallization temperature, larger effective k value, and fewer interface states [1].The ZrHfO/ZnO/ZrHfO tri-layer was sputter deposited on a dilute HF cleaned p-type Si (100) (1015 cm3) wafer in one pumpdown without breaking the vacuum. The ZrHfO layer was sputtered from a Zr/Hf target (12:88 wt%) in Ar/O2 (1:1) at 5 mTorr, 60W for 2 min (bottom) or 10 min (top layer), The ZnO layer was sputtered from a ZnO target in Ar/O2 at 5 mTorr, 60W for 3 min. The tri-layer was treated with a PRTA process of 10 cycles of 800ºC heating-1 second cooling under N2 atmosphere. A control sample that contained only the ZrHfO gate dielectric was also prepared with the same deposition and PRTA process for comparison. The complete MOS capacitor was complete after the aluminum (Al) gate electrode was defined and treated with a post metal annealing (PMA) step at 400ºC under the H2/N2 (1:9) for 5min. The back side of the Si wafer was deposited with an Al contact layer. Charge trapping characteristics were determined from the C-V hysteresis curves.Figure 1 shows TEM cross-sectional views of (a) control and (b) nc-ZnO embedded samples. The ZrHfO layer remains amorphous and a thick amorphous interface layer was formed underneath it. The PRTA treated tri-layer contains discrete nc-ZnO dots, as shown in Fig. 1(b). Separately, the XRD pattern shows that the nc-ZnO has the (100) crystalline structure. The ZrHfO layer is amorphous and the interface layer thickness is about the same as that of the control sample.The control sample, i.e., with the ZrHfO gate dielectric layer, shows very small C-V hysteresis. However, the nc-ZnO embedded sample shows visible C-V hysteresis. Figure 2 shows that when the gate voltage (Vg ) was swept from positive (+Vg ) to negative (-Vg ), i.e., forward, and then to positive (+Vg ), i.e., backward, the gap of the flat band voltages (VFB ’s) was increased. In addition, when swept under the same Vg range, the shift of the VFB in the backward direction is larger than that in the forward direction. Therefore, the charge trapping capacity of the nc-ZnO is dependent on the supply of the amount of charges injected from the substrate.Other charge trapping characteristics, such as the memory windows of the control and nc-ZnO embedded samples as well as the time dependent charge retentions of electrons and holes, will be discussed.[1] Y. Kuo, ECS Trans., 35(3), 13 (2011).[2] Y. Maeda, et al., Appl. Phys. Lett., 59, 3168 (1991).[3] J. Lu, Y. Kuo, J. Yan, and C.-H. Lin, JJAP, 45(34), L901 (2006).[4] C.-H. Yang, Y. Kuo, and C.-H. Lin, APL, 96, 192106 (2010).[5] S. Zhang and Y. Kuo, ECS JSS, 7 (5), Q97 (2018).[6] Y. Kuo, ECS Trans., 66(5), 139 (2015).[7] C.-H. Lin and Y. Kuo, MRS Proc., 1250, G01-08 (2010).[8] Y. Kuo, C.-C. Lin, and S Verkhoturov, 38th IEEE PVSC Proc., 000342 (2011). Figure 1
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Dec 10, 2021
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