XNOR Research Articles

Algorithmic Approach of Electrically Doped Single-walled Cytosine Nanotube-based Biomolecular Logic Gate: A First Principle Paradigm

Biomolecular modeling and its associated analytical software simulation tools have a significant role in the rapid progress of bio-inspired semiconductor technologies. This paper presents the implementation of logic gates using molecular modeling of a cytosine-based single-walled nanotube. Density functional theory in and the nonequilibrium Green’s function-based first-principles approach are used to perform the quantum mechanical calculations for the electronic transmission within the nanotube. The gated cytosine single-walled nanotube shows high current-voltage response during room-temperature operation where the electrode voltage is kept at ± 0.02 V. This is a first attempt towards the circuit-level modeling of logic gates using a cytosine nanotube. The quantum transport phenomenon of this analytical model is investigated using an atomistic software simulation technique. The basic logic gates and XNOR gate are implemented with the study of the current-voltage characteristics. The maximum current observed during the simulation process is 52.6 μA. Moreover, the local device density at different energy levels proves the candidature of cytosine nanotubes as logic gates. The transmission spectrum analysis also confirms the high channel conductivity at the central scattering region of the nanotube.

A Microscale Numerical Analysis of Ex-OR and Ex-NOR Logic Gates by Using Single Plasmonic MZI

This work is focused on a detailed mathematical and numerical simulation–based analysis of Ex-OR and Ex-NOR logic gates at microscale by employing metal-insulator-metal (MIM) plasmonic waveguide–based Mach-Zehnder interferometer (MZI). The geometry of MIM waveguide is designed by considering the air as dielectric material in between silver metallic layers. The bulk plasma frequency and damping constant of silver metallic layers are considered as ωp = 140 × 1014 rad/s and $${\varvec{\gamma}}=$$ 0.4 × 1014 rad/s, respectively. A nonlinear Kerr-material with response in the order of picosecond is employed in linear arms of MZI to switch the phase of optical signals. The design of single MZI is modelled within the footprints of 19 × 3 µm with a high extinction ratio (ER) of 29 dB. The phase change property of MZI is utilized to validate the operation of Ex-OR and Ex-NOR gates. The results suggest that the proposed plasmonic-based logic gates can pave the path for efficient all optical signal processing system.

High-Density Memristor-CMOS Ternary Logic Family

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

Single-bit comparator in quantum-dot cellular automata (QCA) technology using novel QCA-XNOR gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference

Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and energy efficiency along with throughput. For both varieties, we demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarized neural network implementation, we achieve up to twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.

Frequency-domain ultrafast passive logic: NOT and XNOR gates

Electronic Boolean logic gates, the foundation of current computation and digital information processing, are reaching final limits in processing power. The primary obstacle is energy consumption which becomes impractically large, > 0.1 fJ/bit per gate, for signal speeds just over several GHz. Unfortunately, current solutions offer either high-speed operation or low-energy consumption. We propose a design for Boolean logic that can achieve both simultaneously (high speed and low consumption), here demonstrated for NOT and XNOR gates. Our method works by passively modifying the phase relationships among the different frequencies of an input data signal to redistribute its energy into the desired logical output pattern. We experimentally demonstrate a passive NOT gate with an energy dissipation of ~1 fJ/bit at 640 Gb/s and use it as a building block for an XNOR gate. This approach is applicable to any system that can propagate coherent waves, such as electromagnetic, acoustic, plasmonic, mechanical, or quantum.

Signal aware energy efficient approach for low power full adder design with adiabatic logic

Prolonged battery life is the major concern for modern low power electronic devices. Concentrating on this issue, in this paper a new structure of full adder has been proposed. Based on this architecture four new designs of low power full adder have been proposed. Two designs of proposed full adder i.e., A1 and A3 consist of four and three transistors based X-NOR gate respectively. Functionality of these two designs also verified with improved performance by employing diode free adiabatic logic (DFAL) in proposed adders, A2, and A4. Signal aware power efficient inverters have been used for proposed designs. Proposed adder designs are fast and consume less power as compared to the existing adders reported in literature. The proposed designs show a power delay product (PDP) of 0.041 fJ, 0.016 fJ, 0.054 fJ, and 0.047 fJ for adder A1, A2, A3 and, A4 respectively as compared to best reported double pass transistor full adder with 0.061 fJ. The proposed designs also perform well at stringent temperature, capacitance and, frequency conditions. These designs show satisfactory performance at low voltages whereas; the use of adiabatic logic makes these designs energy efficient for low power applications.

Reflective semiconductor optical amplifiers-based all-optical NOR and XNOR logic gates at 120 Gb/s

In this paper, we reported a reflective semiconductor optical amplifier (RSOA), in which the input light propagates and reflects back to the input port after amplifying twice through its active region. The RSOA produces higher gain and lower noise figure at low drive currents with energy-efficient than the conventional SOAs. The RSOA’s features are employed herein to numerically analyze the ultrafast performance of the all-optical NOT-OR (NOR) and Exclusive-NOR (XNOR) logic gates using a dual-RSOAs-based scheme at 120 Gb/s. A comparison between RSOAs- and conventional SOAs-based AO NOR and XNOR gates is made by studying the quality factor (QF) against the critical operational parameters when the effects of the amplified spontaneous emission and the operating temperature are included to obtain more realistic results. Compared to conventional SOAs, the RSOAs allow to achieve more acceptable performance at 120 Gb/s and to render the implementation of the NOR and XNOR gates more feasible.

DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS

This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.

A Low Power Digital Binary Magnitude Comparator Design for Very Large Scale Integration Applications

This paper reports two designs of low power digital binary magnitude comparator based on static complementary CMOS logic style. The designs make use of recently reported latest XNOR gate designs. The comparator designs proposed here are easily scalable for higher order bits and thus highly suitable for VLSI applications. Mathematical equations establishing the relation between input bit width and transistor count of the magnitude comparators have also been derived in this paper. For a 64 bit magnitude comparator, the designs proposed in this paper outperform an existing design by 12.17% and 10.42% in terms of transistor requirement and 14.81% and 11.78% in terms of average power consumption.

Design of Low Power Adder Cell by XOR & XNOR Gate

In under this research article, neoteric circuits for Exclusive OR gate and Exclusive NOR gate are designed. The designed logic is highly refined in terms of power consummation and speed, which are due to minimum CL at the output and low leakage power. We followed six novel hybrids, one bit one full-adder design based on the new Exclusive OR gate and Exclusive NOR (XOR-XNOR) gates. Many Relevant designed logics carries its advantages within aspect relevant to delay power, dissipation power, speed, as well as all that. Within validate the presentation of the introduced design, major SPICE as well as Tanner EDA simulations function as executed. This simulation outcomes, arrange at a 65-nanometer based on hybrid technique process, reveal for the introduced architecture have the best speed and power in contempt of different Full Adder architectures. The proposed design has a minimum power of 0.8 nw & delay of 9.4 ns, which is very optimized & efficient than the reference design. The previous design has 4.08-microwatt power. We customized the design with 22T and change the design methodology to make the results optimized.

RETRACTED ARTICLE: Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP.

Chiral Magnonics: Reprogrammable Nanoscale Spin Wave Networks Based on Chiral Domain Walls.

SummarySpin waves offer promising perspectives as information carriers for future computational architectures beyond conventional complementary metal-oxide-semiconductor (CMOS) technology, owing to their benefits for device minimizations and low-ohmic losses. Although plenty of magnonic devices have been proposed previously, scalable nanoscale networks based on spin waves are still missing. Here, we demonstrate a reprogrammable two-dimensional spin wave network by combining the chiral exchange spin waves and chiral domain walls. The spin-wave network can be extended to two dimensions and offers unprecedented control of exchange spin waves. Each cell in the network can excite, transmit, and detect spin waves independently in the chiral domain wall, and spin-wave logics are also demonstrated. Our results open up perspectives for integrating spin waves into future logic and computing circuits and networks.

Design and Implementation of Electro-Optic 2×2 Switch and Optical Gates using MZI

AbstractMZI switches are well-known devices for high speed communication applications. A lot of researchers have designed MZI switches by using lithium niobate and potassium niobate material. But the major problem of using these type of material includes high insertion losses and required high switching voltage. So, in this research paper we have designed a 2×2 electro-optic switch using optical waveguide designed with Titanium (Ti) diffused in Strontium barium niobate (SBNO3) material which can operate at wavelength of 1.3 um. Results show that the proposed structure gives better output in terms of extinction ratio (=29.9 db) as well as for insertion losses (≤0.018). Further, we have designed various optical gates i. e. XNOR, XOR and AND optical gates and their performance is also evaluated by varying electrode voltages. It is inferred from the results that the proposed model gives better results even in terms of output power which can be used for commercial purpose.

Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

Modelling for triple gate spin‐FET and design of triple gate spin‐FET‐based binary adder

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.

Advanced realization and characterization of directed optical logic gates using electroabsorptive quantum-well-based micro ring resonator

We propose the implementation of directed logic gates using electroabsorptive (EA) quantum-well (QW) based p-i-n diodes embedded in the waveguiding regions of optical microring resonators (MRR). The absorption of the QW incorporated in the MRR configurations varies with respect to the applied field due to the quantum confined stark effect and results in optical switching by shifting the resonant wavelength. The optical logic gates are realized by representing the operands as the applied field on the rings while the operation results of logic gates appears as in the form of light intensities at the output ports of MRR. The proposed configurations are optimized (in terms of coupling coefficient, operating wavelength and applied field) to acheive logic operations such as AND, NAND, XOR, XNOR and Fredkin gates. EA modulation mechanism fails to implement OR and NOR gates on a parallel MRR configuration due to significant Q-factor reduction as the absorption increases with applied field. A novel electroabsorptive triple ring resonator configuration is proposed which can simultaneously realize optical OR as well as AND gate at the output ports.

Hide text depending on the three channels of pixels in color images using the modified LSB algorithm

At the moment, with the great development of information and communications technology, the transfer of confidential and sensitive data through public communications such as the Internet is very difficult to keep them from hackers and attackers. Therefore, it is necessary to work on the development of new and innovative ways to transfer such information and protect it to ensure that it reaches the desired goal. The goal of a new technique to hide information design not only hides the secret message behind the center cover, but it also provides increased security. The most common way to transfer important and confidential data is through embedding it into cover medium files in a way that does not affect the accuracy of the carrier file, which is known as hiding. In this paper, encryption and concealment techniques were used to protect data transferred from attackers. The proposed method relied on encryption of confidential information using the encryption key and the Xnor gate, after which the encrypted information was hidden in a color image using the LSB algorithm. The method of concealment depends on the extraction of chromatic channels of three RGB for each pixel and specifying the channel in which the bit of the encryption message will be hidden. Some metrics have been adopted to measure the quality of the resulting picture after hiding as PSNR and MSE, and achieve good results.

Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructed with 10 transistors based on the optimization of truth tale of a full adder. A 3 transistor X-NOR gate circuit is also used instead of a conventional X-NOR circuit in the self checking path. Adders of size 4 bit and 8 bit are constructed in various technologies. The results show that the proposed structure reduces the transistor over head by almost 47% and 46% for 4bit and 8bit structures respectively. By achieving this much of reduction in area this work could be suggested for higher order VLSI structures like BIST,DCT etc.,

Minimization of digital logic gates and ultra-low power AES encryption core in 180CMOS technology

This work concentrate on the design of low power substitution box architecture with enhanced galois field based transform towards multiplier in advanced cryptographic encryption core. Basic components such as AND, XOR, XNOR are being used for the designing process. Initially tree based XNOR gates are picked up and then the AND gates are replaced by NAND gated with less number of transistor in it. Here, logical method is carried out, which is actually considered as better method for re-sizing of transistor. This will further decrease the overall delay and power consumption. The less delay can be obtained by 4-input XOR gate architecture. The implementation results with an 180 nm CMOS standard library show that the proposed AES core can reduce the area and power consumption significantly.