Design of Low Power Adder Cell by XOR & XNOR Gate

Abstract

In under this research article, neoteric circuits for Exclusive OR gate and Exclusive NOR gate are designed. The designed logic is highly refined in terms of power consummation and speed, which are due to minimum CL at the output and low leakage power. We followed six novel hybrids, one bit one full-adder design based on the new Exclusive OR gate and Exclusive NOR (XOR-XNOR) gates. Many Relevant designed logics carries its advantages within aspect relevant to delay power, dissipation power, speed, as well as all that. Within validate the presentation of the introduced design, major SPICE as well as Tanner EDA simulations function as executed. This simulation outcomes, arrange at a 65-nanometer based on hybrid technique process, reveal for the introduced architecture have the best speed and power in contempt of different Full Adder architectures. The proposed design has a minimum power of 0.8 nw & delay of 9.4 ns, which is very optimized & efficient than the reference design. The previous design has 4.08-microwatt power. We customized the design with 22T and change the design methodology to make the results optimized.