Xilinx Virtex-5 Field Programmable Gate Array Research Articles

A FPGA-based state space controller

For many years digital controllers have been implemented using microprocessors, microcontrollers, digital signal processors etc. Recently, field programmable gate arrays (FPGA) is found to be an alternative because of its high processing speed. In this context, this paper presents the implementation of state space controller (SSC) on FPGA. SSC contains an observer to estimate the system unknown states variables. Matrix multiplications involved in this estimation take most of the computation time of the controller. In order to make SSC much more competent for controlling fast dynamic systems, a new FPGA based parallel architecture is proposed. The reduction in computation time with optimal hardware resources is achieved by developing an efficient multistage matrix multiplication algorithm (MMM). The performance of FPGA-based SSC is validated by implementing it in an inverted pendulum control system. The design is mapped on xilinx virtex-5 FPGA device with a maximum frequency of 449.438MHz.

FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field

Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.

High-Speed and Adaptive FPGA-Based Privacy Amplification in Quantum Key Distribution

Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many high-speed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.

A real-time, high-accuracy, hardware-based integrated parameter estimator for deep space navigation and planetary radio science experiments

Real-time, high-accuracy frequency-phase estimation is the critical mission of Doppler tracking, which is a primary technique for deep space spacecraft navigation and planetary radio science experiments. Usually, the analog intermediate frequency signal is digitalized and converted to baseband by signal processing hardware platforms called digital back-ends (DBEs) and parameter estimation is performed by extra high performance computers. In this paper, a novel real-time, high-accuracy parameter estimator called a hardware-based integrated parameter estimator (HIPE) is proposed and implemented inside DBEs. An adaptive frequency tracker is proposed to make the initial signal detection, frequency tracking, and data reduction. Then a parameter estimation is sequentially obtained by a modified dechirp technique and a high-resolution spectral analysis technique called spec-zooming. Further, a folding architecture is designed to save hardware resources when realizing spec-zooming in a field programmable gate array (FPGA). An example design is deployed on a DBE with Xilinx Virtex-6 FPGA and an ARM processor. The performance is verified by X-band observations of Mars Express (MEX) and New Horizons (NH). Under an integration time of 1 s, HIPE only takes 2.2 ms to process single-channel baseband data and provides frequency accuracies of 7 mHz and 30 mHz for the tested MEX and NH data. HIPE is implemented inside DBE, so the extra computer is no longer required and the pressure of data transmission or storage is greatly relieved. It could easily be extended to parallel multi-channel, real-time processing and would be a powerful method for Doppler measurement in deep space exploration missions, such as the Chinese mission to Mars to be undertaken by 2020.

A Reconfigurable Hardware Architecture for Principal Component Analysis

Principal component analysis (PCA) is one of the widely used techniques for dimensionality reduction in multivariate statistical analysis. This article presents an efficient architecture design and implementation of the PCA algorithm on a field-programmable gate array (FPGA). The designed reconfigurable architecture is modeled in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The PCA architecture supports input dataset matrices with parameterizable dimensions. The synthesizable model of the PCA architecture is modeled in Verilog hardware description language, and its cycle-accurate and bit-true simulation results are verified against its software simulation models. The characteristics and implementation results of the PCA architecture on a Xilinx Virtex-7 FPGA and in a standard 45-nm CMOS technology are presented. The execution times of the implemented PCA system on the FPGA for different data sizes are compared with those of the graphics processing unit and general-purpose processor implementations. To the best of our knowledge, this work is the first high-throughput design and implementation of the reconfigurable PCA architecture, including both the learning and mapping phases, on a single FPGA.

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

Static random-access memory (SRAM)-based ternary content-addressable memory (TCAM), an alternative to traditional TCAM, where inclusion of SRAM improves the memory access speed, scalability, cost, and storage density compared to conventional TCAM. In order to confidently use the SRAM-based TCAMs in application, an update module (UM) is essential. The UM replaces the old TCAM contents with fresh contents. This letter proposes a fast update mechanism for an SRAM-based TCAM and implements it on Xilinx Virtex-6 field-programmable gate array. To the best of authors’ knowledge, this is the first ever proposal on content-update-module in an SRAM-based TCAM, which consumes least possible clock cycles to update a TCAM word.

High‐throughput and compact reconfigurable architectures for recursive filters

This study presents various high-throughput reconfigurable architectures and their hardware implementation characteristics for infinite impulse response (IIR) filters. It is known that finite word length effects can be alleviated, to some extent, by realising a high-order IIR filter using the cascade of lower-order filter sections. The authors utilise the cascade structure of the first-order and second-order filters and apply a set of optimisation techniques, such as cutset retiming, look-ahead transformations, and interleaving for high-throughput realisations of IIR filters. Since the cascade structure may require a relatively large number of computational resources and storage elements, which depends linearly on the number of sections, the authors also present a filter processor architecture for the compact implementation of IIR filters. Filter architectures are developed in the fully parameterisable fixed-point representation and verified against their synthesisable Verilog descriptions. The authors present the implementation results of the transformed filter architectures on a Xilinx Virtex-7 field-programmable gate array (FPGA). To the best of their knowledge, this is the first presentation of various high-throughput and compact IIR filter architectures and their FPGA implementation characteristics.

Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations

Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure to achieve an efficient use of resources. A folding operation requires a permutation block, which is typically implemented using either permutation logic or address generation. Addressing schemes offer resource-efficient advantages when compared to permutation logic. We propose a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in FFT cores. To support this procedure, we develop a mathematical formulation based on Kronecker products algebra for address sequence generation and data flow pattern in FFT core computations, a well-defined procedure for scaling address generation schemes, and an improved approach in the overall automated generation of FFT cores. We have also performed an analysis and comparison of the proposed hardware design performance with respect to a similar strategy reported in the recent literature in terms of clock latency, performance, and hardware resources. Evaluations were carried on a Xilinx Virtex-7 FPGA (Field Programmable Gate Array) used as implementation target.

The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection

Sparse signal recovery becomes extremely challenging for a variety of real-time applications. In this paper, we improve the orthogonal matching pursuit (OMP) algorithm based on parallel correlation indices selection mechanism in each iteration and Goldschmidt algorithm. Simulation results show that the improved OMP algorithm with a reduced number of iterations and low hardware complexity of matrix operations has higher success rate and recovery signal-to-noise-ratio (RSNR) for sparse signal recovery. This paper presents an efficient complexvalued system hardware architecture of the recovery algorithm for analog-to-information structure based on compressive sensing. The proposed architecture is implemented and validated on the Xilinx Virtex6 field-programmable gate array (FPGA) for signal reconstruction with N = 1024, K = 36, and M = 256. The implementation results showed that the improved OMP algorithm achieved a higher RSNR of 31.04 dB compared with the original OMP algorithm. This synthesized design consumes a few percentages of the hardware resources of the FPGA chip with the clock frequency of 135.4 MHZ and reconstruction time of 170 μs, which is faster than the existing design.

MIMO Detector for LTE/LTE-A Uplink Receiver

We propose a carefully selected receiver structure, detector and detector implementation architecture for multiple-input multiple-output (MIMO) uplink base station receiver for fourth generation (4G) wireless cellular systems. First, we compare different receiver algorithms and structures for single-carrier frequency-division multiple access (SC-FDMA) uplink transmission to get a good understanding of the performance and complexity of these algorithms and their suitability for practical realization. One of those structures, namely the frequency domain MMSE equalization with sphere detection (SD), is proposed for implementation. The receiver consists of separate stages for inter-symbol interference (ISI) and inter-antenna interference (IAI) mitigation in frequency selective MIMO channels. Frame error rate (FER) performance is studied via simulations in realistic wireless channels and practical system parameters. K-best SD is selected as a detector algorithm for this receiver. There are several publications proposing a sort-free architecture for tree search type of detectors. Both a conventional K-best architecture and a sort-free architecture are implemented on a Xilinx Virtex-6 field-programmable gate array (FPGA) using High Level Synthesis (HLS) tool. Both architectures support 4 × 4 MIMO with 64-level modulation (64-QAM). Complexity results confirm that avoiding the sorter is not always recommended. The benefit of sort-free architecture depends on the system parameters.

Multiplier-Less Stream Processor for 2D Filtering in Visual Search Applications

A new 2D convolution-based filter is presented, which is specifically designed to improve visual search applications. It exploits a new radix-3 partitioning method of integer numbers, derived from the weight partition theory, which allows substituting multipliers with simplified floating point (FP) adders, working on 32-b FP filter coefficients. The memory organization allows elaborating the incoming data in raster scan order, as those directly provided by an acquisition source, without frame buffers and additional aligning circuitry. Compared with the existent literature, built around conventional arithmetic circuitry, the proposed design achieves state-of-the-art performances in the reduction of the mapped physical resources and elaboration velocity, achieving a critical path delay of about 4.5 ns both with a Xilinx Virtex-7 field-programmable gate array and CMOS 90-nm std_cells.

FPGA-Based Implementation of Size-Adaptive Privacy Amplification in Quantum Key Distribution

In a quantum key distribution (QKD) system, privacy amplification (PA) is an essential procedure that can effectively eliminate the leaked information to an eavesdropper and distill a secret key. The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. The implementation of the PA reduces significantly the required number of FPGA Block RAMs. Meanwhile, it automatically adapts to different lengths of input and output blocks. Finally, we verified the correctness and high-speed of the algorithm when implemented in a Xilinx Virtex-7 FPGA.

LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

Binary content-addressable memory (BiCAM) is a popular high speed search engine in hardware, which provides output typically in one clock cycle. But speed of CAM comes at the cost of various disadvantages, such as high latency, low storage density, and low architectural scalability. In addition, field-programmable gate arrays (FPGAs), which are used in many applications because of its advantages, do not have hard IPs for CAM. Since FPGAs have embedded IPs for random-access memories (RAMs), several RAM-based CAM architectures on FPGAs are available in the literature. However, these architectures are especially targeted for ternary CAMs, not for BiCAMs; thus, the available RAM-based CAMs may not be fully beneficial for BiCAMs in terms of architectural design. Since modern FPGAs are enriched with logical resources, why not to configure them to design BiCAM on FPGA? This letter presents a logic-based high performance BiCAM architecture (LH-CAM) using Xilinx FPGA. The proposed CAM is composed of CAM words and associated comparators. A sample of LH-CAM of size ${64\times 36}$ is implemented on Xilinx Virtex-6 FPGA. Compared with the latest prior work, the proposed CAM is much simpler in architecture, storage efficient, reduces power consumption by 40.92%, and improves speed by 27.34%.

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

A FPGA-based Hardware Architecture for Real-time Texture Classification Using Local Binary Patterns

Local Binary Pattern (LBP) is a simple yet efficient texture operator which has become a popular approach in texture classification. In this paper, we propose a novel hardware architecture for texture classification algorithms based on local binary patterns that can be executed efficiently on a field-programmable gate arrays (FPGAs). A new memory structure and window operations have been used in this hardware design to accelerate images processing. The new architecture is implemented on Xilinx Virtex-6 FPGA. The experiments show that this new method exhibits more efficient execution compared with standard implementations based on central processing units and graphics processing units.

FPGA-based SOC for hardware implementation of a local histogram-based video shot detector

In this paper, we present a video application example and its implementation in a reconfigurable system-on-chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target hardware system. They also show high execution time efficiency and can reach an important bandwidth that can support the most recent high-resolution video formats with a high rate of frames per second. A complete SOC-based demonstration for video summarization based on the LH is also developed. It includes the LH extraction, shot boundary detection, and key frame visualization.

Secure and Dependable NoC-Connected Systems on an FPGA Chip

The growing reliance on intellectual properties exposes systems on chip (SoCs) to many security vulnerabilities and is raising more and more concerns. At the same time, with the quick increase in chip density and deep scaling of feature size, current billion-transistor chip designs introduce more challenges to manufacturing fault-free chips. In this paper, we propose an integrated run-time solution for both security and fault tolerance of field-programmable gate arrays (FPGA)-based SoCs through digital signatures, live monitoring, adaptive routing, and partial reconfiguration supported by an in-house-developed network on chip, X-Network. Our X-Network reduces the ratio of required routers versus processing elements with better performance, and more importantly, offers more flexibility than conventional networks to facilitate fault tolerance and security designs. A multiplexed Montgomery modular multiplication architecture is used to increase the speed of the Rivest-Shamir-Adleman algorithm. The design has been implemented and tested on a Xilinx Virtex-6 FPGA development board. Experimental results show that even if up to 20% of the links in the network are faulty, our reconfigurable architecture and algorithm manage to route packets around such faults, and deliver them to their destinations in a relatively low latency. Unlike conventional fault-tolerant methods that usually require resource redundancy, our design does not incur significant area or speed degradation. The resource overhead for both security and fault-tolerant features is around 10% more lookup tables.

A Massively Parallel Approach to Real-Time Bearing Fault Detection Using Sub-Band Analysis on an FPGA-Based Multicore System

The fact that rolling element bearing faults have an amplitude-modulating effect on their characteristic frequencies calls for sub-band analysis to determine an optimal sub-band signal that contains intrinsic information about bearing faults. In this regard, it is significant to accurately assess the presence of a bearing's abnormal symptoms. Hence, a bearing abnormality index (BAI) that properly quantifies how much information a sub-band signal contains about bearing faults is presented. Additionally, to facilitate real-time sub-band analysis based on the BAI, a massively parallel approach is introduced, where the approach involves the use of the multicore system. Likewise, the multicore system supports high-performance computing by exploiting 128 processing elements operating at 200 MHz in a Xilinx Virtex-7 field-programmable gate array (FPGA) device.

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.