Xilinx Virtex-5 FPGA Research Articles

FPGA implementation of 1000base-x Ethernet physical layer core

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

An asynchronous mesh NoC based booth multiplication

The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide-used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8-bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex-7 FPGA development board.

Design and Digital Implementation of Fast and Recursive DCT II–IV Algorithms

Using the proposed factorizations of discrete cosine transform (DCT) matrices, fast and recursive algorithms are stated. In this paper, signal flow graphs for the n-point DCT II and DCT IV algorithms are introduced. The proposed algorithms yield exactly the same results as with standard DCT algorithms but are faster. The arithmetic complexity and stability of the algorithms are explored, and improvements of these algorithms are compared with previously existing fast and stable DCT algorithms. A parallel hardware computing architecture for the DCT II algorithm is proposed. The computing architecture is first designed, simulated, and prototyped using a 40-nm Xilinx Virtex-6 FPGA and thereafter mapped to custom integrated circuit technology using 0.18- $$\upmu $$ m CMOS standard cells from Austria Micro Systems. The performance trade-off exists between computational precision, chip area, clock speed, and power consumption. This trade-off is explored in both FPGA and custom CMOS implementation spaces. An example FPGA implementation operates at clock frequencies in excess of 230 MHz for several values of system word size leading to real-time throughput levels better than 230 million 16-point DCTs per second. Custom CMOS-based results are subject to synthesis and place-and-route steps of the design flow. Physical silicon fabrication was not conducted due to prohibitive cost.

Hardware implementation of adaptive feedback based reversible image watermarking for image processing application

This paper presents a reversible image watermarking (RIW) method including an adaptive feedback part based on difference expansion (DE). With respect to some parameters of the image, peak signal to noise ratio (PSNR), the highest payload capacity and the corresponding embedding threshold are spontaneously calculated by using the proposed adaptive feedback-based reversible Image watermarking (AFRIW). The payload capacity for data embedding is briefly explained. The machinery part of the adaptive feedback for controlling the payload capacity is presented. Software verification of three cover images is presented. Based on some image parameters, the comparative result between the proposed AFRIW algorithm and DE-based RIW method is presented. This paper also presents the VLSI architecture of this proposed algorithm for RIW. The proposed architecture has been implemented using VIVADO 2016.2 based on Xilinx Virtex-7 FPGA and Zynq device platforms. The software implementation results clearly demonstrated that the AFRIW method provides higher PSNR than the DE-based RIW method. The hardware implementation results indicate that the proposed algorithm has low timing complexity over other existing feedback based RIW algorithms which in turn provide higher speed.

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports

In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Player tracking using vision systems is a very challenging task due to the nature of sports games, which includes severe and frequent interactions (e.g. occlusions) between the players. Additionally, these vision systems have high computational demands since they require processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rate. As a result, most of the existing systems based on general-purpose computers are not able to perform online real-time player tracking, but track the players offline using pre-recorded video files, limiting, e.g., direct feedback on the player performance during the game. In this paper, we present a reconfigurable system to track the players in indoor sports automatically and without user interaction. The proposed system performs real-time processing of the incoming video streams from the cameras, achieving online player tracking. The teams are identified, and the players’ positions are detected based on the colors of their jerseys. FPGA technology is used to handle the compute-intensive vision processing tasks by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing an online real-time system. While the pixel processing is performed in the FPGA, the less compute-intensive player tracking is performed on a general purpose computer. The maximum achieved frame rate for the FPGA implementation is 96.7 fps using a mature Xilinx Virtex-4 FPGA, and can be increased to 136.4 fps using a Xilinx Virtex-7 device. The Player tracking requires an average time of 2.5 ms per frame in the host-PC. As a result, the proposed reconfigurable system supports a maximum frame rate of 78.9 fps using two cameras with a resolution of 1392 × 1040 pixels each. Our results show that the achieved average precision and recall for player detection are up to 84.02% and 96.6%, respectively. Including player tracking, the achieved average precision and recall are up to 94.85% and 94.72%, respectively. Using the proposed FPGA implementation, a speedup by a factor of 15.2 is achieved compared to an OpenCV-based software implementation on a PC equipped with a 2.93 GHz Intel i7-870 CPU.

FPGA-Based On-Board Geometric Calibration for Linear CCD Array Sensors.

With increasing demands in real-time or near real-time remotely sensed imagery applications in such as military deployments, quick response to terrorist attacks and disaster rescue, the on-board geometric calibration problem has attracted the attention of many scientists in recent years. This paper presents an on-board geometric calibration method for linear CCD sensor arrays using FPGA chips. The proposed method mainly consists of four modules—Input Data, Coefficient Calculation, Adjustment Computation and Comparison—in which the parallel computations for building the observation equations and least squares adjustment, are implemented using FPGA chips, for which a decomposed matrix inversion method is presented. A Xilinx Virtex-7 FPGA VC707 chip is selected and the MOMS-2P data used for inflight geometric calibration from DLR (Köln, Germany), are employed for validation and analysis. The experimental results demonstrated that: (1) When the widths of floating-point data from 44-bit to 64-bit are adopted, the FPGA resources, including the utilizations of FF, LUT, memory LUT, I/O and DSP48, are consumed at a fast increasing rate; thus, a 50-bit data width is recommended for FPGA-based geometric calibration. (2) Increasing number of ground control points (GCPs) does not significantly consume the FPGA resources, six GCPs is therefore recommended for geometric calibration. (3) The FPGA-based geometric calibration can reach approximately 24 times faster speed than the PC-based one does. (4) The accuracy from the proposed FPGA-based method is almost similar to the one from the inflight calibration if the calibration model and GCPs number are the same.

An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM

This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route Placed design.

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed design is scalable with the transform length and the calculable number of the DFT bins, and can provide high throughput for a single bin evaluation. The paper also presents the comparison of the conventional and the modulated SDFT architectures based on CORDIC algorithm in terms of the angle-approximation and the truncation errors. The proposed design is synthesized on the Xilinx Virtex-6 FPGA platform and is implemented in ASIC using 90 nm standard cell library.

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation

Stereo vision is a methodology to obtain depth in a scene based on the stereo image pair. In this paper, we introduce a discrete wavelet transform (DWT)-based methodology for a state-of-the-art disparity estimation algorithm that resulted in significant performance improvement in terms of speed and computational complexity. In the initial stage of the proposed algorithm, we apply DWT to the input images, reducing the number of samples to be processed in subsequent stages by 50%, thereby decreasing computational complexity and improving processing speed. Subsequently, the architecture has been designed based on this proposed methodology and prototyped on a Xilinx Virtex-7 FPGA. The performance of the proposed methodology has been evaluated against four standard Middlebury Benchmark image pairs viz. Tsukuba , Venus , Teddy , and Cones . The proposed methodology results in the improvement of about 44.4% cycles per frame, 52% frames/s, and 61.5% and 59.6% LUT and register utilization, respectively, compared with state-of-the-art designs.

Implementation of CS coefficient calculation based on dual‐operator engines in multimode spaceborne SAR imaging systems

To provide an optimised implementation aimed at calculating the chirp scaling (CS) coefficients used in state-of-the-art spaceborne synthetic aperture radar (SAR) imaging systems. Built on the core concept of breaking down the CS coefficient calculation into basic operations, we propose a new architecture that adopts a dual-operator engine as the basic processing unit and seeks to optimise the switching network of operator engines through an appropriately interconnected grouping of various calculations. A wide variety of SAR imaging architectures based on fast Fourier transformation-CS operations may benefit from this work. The proposed architecture is implemented in a Xilinx Virtex-7 FPGA process; a comparison between test results and results obtained from an off-the-shelf counterpart confirms the efficacy of the proposed architecture.

Online Adaptation and Energy Minimization for Hardware Recurrent Spiking Neural Networks

The Liquid State Machine (LSM) is a promising model of recurrent spiking neural networks that provides an appealing brain-inspired computing paradigm for machine-learning applications such as pattern recognition. Moreover, processing information directly on spiking events makes the LSM well suited for cost- and energy-efficient hardware implementation. In this article, we systematically present three techniques for optimizing energy efficiency while maintaining good performance of the proposed LSM neural processors from both an algorithmic and hardware implementation point of view. First, to realize adaptive LSM neural processors, thus boost learning performance, we propose a hardware-friendly Spike-Timing Dependent Plastic (STDP) mechanism for on-chip tuning. Then, the LSM processor incorporates a novel runtime correlation-based neuron gating scheme to minimize the power dissipated by reservoir neurons. Furthermore, an activity-dependent clock gating approach is presented to address the energy inefficiency due to the memory-intensive nature of the proposed neural processors. Using two different real-world tasks of speech and image recognition to benchmark, we demonstrate that the proposed architecture boosts the average learning performance by up to 2.0% while reducing energy dissipation by up to 29% compared to a baseline LSM with little extra hardware overhead on a Xilinx Virtex-6 FPGA.

High frequency implementation of cryptographic hash function Keccak-512 on FPGA devices

Cryptographic hash functions have an important role in numerous cryptographic mechanisms like computing digital signatures, checking data integrity, storing passwords and generating random numbers. Due to the cryptanalysis attacks on hash functions, NIST expressed its need to a new resistant hash function by announcing a public competition, this competition made Keccak hash function the new secure hash algorithm SHA-3. This new SHA-3 proved its strengths against recent attacks. However it has to be implemented efficiently in order to keep its resistance. In other words, an efficient FPGA design of hash functions is needed be it increasing frequency, minimising area consumption, or increasing throughput. In this paper we have focused on increasing frequency of the Keccak-512, and we have achieved 401.2 MHz as a maximum frequency, and 9.62 Gbps as a throughput. The proposed design has been implemented in Xilinx Virtex-5 and Virtex-6 FPGA devices and compared to existing FPGA implementations.

High frequency implementation of cryptographic hash function Keccak-512 on FPGA devices

Cryptographic hash functions have an important role in numerous cryptographic mechanisms like computing digital signatures, checking data integrity, storing passwords and generating random numbers. Due to the cryptanalysis attacks on hash functions, NIST expressed its need to a new resistant hash function by announcing a public competition, this competition made Keccak hash function the new secure hash algorithm SHA-3. This new SHA-3 proved its strengths against recent attacks. However it has to be implemented efficiently in order to keep its resistance. In other words, an efficient FPGA design of hash functions is needed be it increasing frequency, minimising area consumption, or increasing throughput. In this paper we have focused on increasing frequency of the Keccak-512, and we have achieved 401.2 MHz as a maximum frequency, and 9.62 Gbps as a throughput. The proposed design has been implemented in Xilinx Virtex-5 and Virtex-6 FPGA devices and compared to existing FPGA implementations.

Fast Amplitude Estimation of Harmonics Using Undecimated Wavelet Packet Transform and Its Hardware Implementation

Accurate and fast estimation of time-varying harmonics are essential requirements for online monitoring, analysis, and control of electrical power system. This paper presents a fast algorithm based on the undecimated wavelet packet transform (UWPT) to estimate the amplitude of fundamental and harmonic components of stationary as well as a time-varying power signal. The UWPT uses only one cycle of the fundamental frequency for precise measurement of time-varying harmonics while their amplitude has been determined accurately utilizing the time-invariant property of the UWPT. The robustness and accuracy of the proposed technique have been investigated on synthetic as well as experimental test signals using MATLAB tool. Further, the UWPT algorithm has also been implemented on the Xilinx Virtex-6 FPGA ML-605 board, using XSG/ISE design suite 14.2 and its performance, in terms of hardware accuracy, resource utilization as well as timing requirements have been tested using the experimental test signal.

FPGA-based Implementation of Maximum Power Point Tracking of Solar Cell

This article describes the FPGA based implementation of Maximum Power Point Tracking (MPPT) using Perturbation and Observation (P & O) algorithms for solar cell. This work has been organized in two parts. The complete Maximum Power Point Tracking (MPPT) system model was developed in MATLAB/Simulink environment for functionality verification in the first part. It has been observed from the results which show that maximum power is extracted at the load from PV panel. The second part is to design of P & O algorithm from VHDL code. The designed P & O algorithm was synthesized in Xilinx ISE 14.2 software with small commercial FPGA devices i.e. KINTEX-7 and VIRTEX-5. That designed algorithm was simulated using vector waveform file in FPGA tools. Also, the synthesized results were compared on the basis of area-performance-power obtained through summary of both KINTEX-7 and VIRTEX-5 Xilinx FPGA devices. This work is highly beneficial in real time implementation of algorithm for effective performance.

FPGA-based Implementation of Maximum Power Point Tracking of Solar Cell

This article describes the FPGA based implementation of Maximum Power Point Tracking (MPPT) using Perturbation and Observation (P & O) algorithms for solar cell. This work has been organized in two parts. The complete Maximum Power Point Tracking (MPPT) system model was developed in MATLAB/Simulink environment for functionality verification in the first part. It has been observed from the results which show that maximum power is extracted at the load from PV panel. The second part is to design of P & O algorithm from VHDL code. The designed P & O algorithm was synthesized in Xilinx ISE 14.2 software with small commercial FPGA devices i.e. KINTEX-7 and VIRTEX-5. That designed algorithm was simulated using vector waveform file in FPGA tools. Also, the synthesized results were compared on the basis of area-performance-power obtained through summary of both KINTEX-7 and VIRTEX-5 Xilinx FPGA devices. This work is highly beneficial in real time implementation of algorithm for effective performance.

Design and Analysis of an Efficient Repository System for Protein Coefficients in Systolic Array-Based Architecture by Using Xilinx Virtex-5 FPGA

Design and Analysis of an Efficient Repository System for Protein Coefficients in Systolic Array-Based Architecture by Using Xilinx Virtex-5 FPGA

Service-Oriented Architecture on FPGA-Based MPSoC

The integration of software services-oriented architecture (SOA) and hardware multiprocessor system-on-chip (MPSoC) has been pursued for several years. However, designing and implementing a service-oriented system for diverse applications on a single chip has posed significant challenges due to the heterogeneous architectures, programming interfaces, and software tool chains. To solve the problem, this paper proposes SoSoC, a service-oriented system-on-chip framework that integrates both embedded processors and software defined hardware accelerators s as computing services on a single chip. Modeling and realizing the SOA design principles, SoSoC provides well-defined programming interfaces for programmers to utilize diverse computing resources efficiently. Furthermore, SoSoC can provide task level parallelization and significant speedup to MPSoC chip design paradigms by providing out-of-order execution scheme with hardware accelerators. To evaluate the performance of SoSoC, we implemented a hardware prototype on Xilinx Virtex5 FPGA board with EEMBC benchmarks. Experimental results demonstrate that the service componentization over original version is less than 3 percent, while the speedup for typical software Benchmarks is up to 372x. To show the portability of SoSoC, we implement the convolutional neural network as a case study on both Xilinx Zynq and Altera DE5 FPGA boards. Results show the SoSoC outperforms state-of-the-art literature with great flexibility.

Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware

In this paper, we present a fast implementation for QC-MDPC Niederreiter encryption. Existing high-speed implementations are considerably resource involving but the solution we propose here mitigates such situation while maintaining the high throughputs. In particular, new arithmetic for lightweight Hamming weight computation and a fast sorting network for MDPC decoding are proposed. A novel constant weight coding unit is proposed to enable standard asymmetric encryptions. For now, the design presented in this work is the fastest one of existing QC-MDPC code based encryptions in the public domain. The area-time product of this work drops by at least 53 percent compared to previous fast speed designs of QC-MDPC based encryptions. It is shown for instance that our implementation of encrypting engine can sign one encryption in 3.86 $\mu s$ on a Xilinx Virtex-6 FPGA with 3371 slices. Our iterative decrypting engine can decrypt one ciphertext in 114.64 $\mu s$ with 5271 slices and our faster non-iterative decrypting engine can decrypt in 65.76 $\mu s$ with 8781 slices.