Xilinx Virtex-5 FPGA Research Articles

Practical Multituple Packet Classification Using Dynamic Discrete Bit Selection

Multituple packet classification is one of the key technologies, and often the performance bottleneck in modern network devices. Devices such as firewalls demand fast packet classification on very complicated rule sets of large size, which is still challenging today. This paper proposes a practical packet classification algorithm named dynamic discrete bit selection (D2 BS), which achieves high classification speed while requiring low storage. D2 BS employs dynamic heuristic schemes at bit level, to explore the inherent characteristics of the rule sets. D2BS has been implemented on various platforms including Intel-architecture, multicore network processor, and FPGA, and is compared with the state-of-the-art solutions. Experimental results on real-life rule sets show that the memory storage required by D2BS is at least one to two orders of magnitude lower than that of the existing work, while the speed is much higher. With 64-byte Ethernet packet and 10K size ACL rule set, D2BS achieves a throughput over 10 Gbps on Cavium OCTEON CN5860 multicore network processor and over 135 Gbps on Xilinx Virtex-5 FPGA, which outperforms the existing work under the same test environment. All results promise that D2BS is a highly practical solution to satisfy vigorous requirements.

FPGA Implementation of RSA Encryption Algorithm for E-Passport Application

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. Thedesign runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Optimization of the Multi-Spectral Euclidean Distance calculation for FPGA-based spaceborne systems

Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally-expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, an FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

Exploiting Coarse-grained Parallelism in Multi-transform Architectures for H.264/AVC High Profile Codecs

A parallel Multi-Transform Architecture (MTA) for the computation of the 2-D transforms adopted in modern digital video standards is proposed in this paper. This hardware structure can be dynamically configured to efficiently compute either one transform of size N × N ,o rk different transforms of size N k × N k in simultaneous, where N ∈ N and k = 2 i with i = 1, ..., lo g2 N − 1. The advanta ges offered by the proposed parallel architecture were assessed by implementing in a Xilinx Virtex-7 FPGA a proof-of-concept t ransform core compliant with the High Profiles of the H.264/AVC standard. The obtained results show that such processing structu re is capable of achieving real-time operation for video sequences in the 8k Ultra High Definition Television (UHDTV) format (7680 × 4320 @ 30 fps). In addition, these results also demonstrate that the proposed parallel MTA allows to, at least, double both the throughput and the hardware efficiency of the implemented transform cores, when compared to the original design of the archi tecture. c

Development and testing of an upgrade to the CMS level-1 calorimeter trigger

When the LHC resumes operation in 2015, the higher centre-of-mass energy and high-luminosity conditions will require significantly more sophisticated algorithms to select interesting physics events within the readout bandwidth limitations. The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps. The upgrade will improve the energy and position resolution of physics objects, enable much improved isolation criteria to be applied to electron and tau objects and facilitate pile-up subtraction to mitigate the effect of the increased number of interactions occurring in each bunch crossing. The design of the upgraded system is summarised with particular emphasis placed on the results of prototype testing and the experience gained which is of general application to the design of such systems.

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of sizem×n, where4≤n≤8andm≥nby dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

Hardware Architecture for Video Authentication Using Sensor Pattern Noise

Digital camera identification can be accomplished based on sensor pattern noise, which is unique to a device, and serves as a distinct identification fingerprint. Camera identification and authentication have formed the basis of image/video forensics in legal proceedings. Unfortunately, real-time video source identification is a computationally heavy task, and does not scale well to conventional software implementations on typical embedded devices. In this paper, we propose a hardware architecture for source identification in networked cameras. The underlying algorithms, an orthogonal forward and inverse discrete wavelet transform and minimum mean square error-based estimation, have been optimized for 2-D frame sequences in terms of area and throughput performance. We exploit parallelism, pipelining, and hardware reuse techniques to minimize hardware resource utilization and increase the achievable throughput of the design. A prototype implementation on a Xilinx Virtex-6 FPGA device was optimized with a resulting throughput of 167 MB/s, processing 30 640 × 480 video frames in 0.17 s.

A low energy adaptive motion estimation hardware for H.264 multiview video coding

Multiview Video Coding (MVC) is the process of efficiently compressing stereo (2 views) or multiview video signals. The improved compression efficiency achieved by H.264 MVC comes with a significant increase in computational complexity. Temporal prediction and inter-view prediction are the most computationally intensive parts of H.264 MVC. Therefore, in this paper, we propose novel techniques for reducing the amount of computations performed by temporal and inter-view predictions in H.264 MVC. The proposed techniques reduce the amount of computations performed by temporal and inter-view predictions significantly with very small PSNR loss and bitrate increase. We also propose a low energy adaptive H.264 MVC motion estimation hardware for implementing the temporal and inter-view predictions including the proposed computation reduction techniques. The proposed hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 30∗8=240 frames per second of CIF (352×288) size 8 view video sequence or 30∗2=60 frames per second of VGA (640×480) size stereo (2 views) video sequence. The proposed techniques reduce the energy consumption of this hardware significantly.

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

In this paper, a new methodology for speeding up edge and line detection algorithms is presented, achieving improved performance over the state of the art software library OpenCV (speedup from 1.35 up to 2.22) and other conventional implementations, in both general and embedded processors, by reducing the number of load/store and arithmetic instructions, the number of data cache accesses and data cache misses in memory hierarchy and the algorithm memory size. This is achieved by fully exploiting the combination of the software and hardware parameters which are considered simultaneously as one problem and not separately. Furthermore, the edge and line detection algorithms have been simplified for a computer vision application in a Virtex-5 Xilinx FPGA using Microblaze soft processor (detection and measurement of flow fronts in a microfluid device); it achieves speedup up to 660 times in comparison with conventional software implementations.

The CMS Modular Track Finder boards, MTF6 and MTF7

To accommodate the increase in energy and luminosity of the upgraded LHC, the CMS Endcap Muon Level 1 Trigger system has to be significantly modified. To provide the best track reconstruction, the Trigger system must now import all available trigger primitives generated by Cathode Strip Chambers and by other regional subsystems, such as Resistive Plate Chambers. In addition to massive input bandwidth, this also requires a significant increase in logic and memory resources.To satisfy these requirements, a new Sector Processor unit for muon track finding is being designed. This unit follows the micro-TCA standard recently adopted by CMS. It consists of three modules. The Core Logic module houses the large FPGA that contains the processing logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Look-Up Table module contains a large amount of low-latency memory that is used to assign the final transverse momentum of the muon candidate tracks. The name of the unit — Modular Track Finder — reflects the modular approach used in the design.Presented here are the details of the hardware design of the prototype unit based on Xilinx's Virtex-6 FPGA family, MTF6, as well as results of the conducted tests. Also presented are plans for the pre-production prototype based on the Virtex-7 FPGA family, MTF7.

Experience powering Xilinx Virtex-7 FPGAs

The MP7 processor card is an all-optical signal processor based on mid-range Xilinx Virtex-7 FPGAs (XC7VX485T or XC7VX690T) in a 1927-pin package. The current version of the card uses the large serial bandwidth of these FPGAs to provide a 0.75+0.75Tbps bidirectional interface, although changes are currently being implemented to push the bandwidth to 0.94+0.94Tbps. The MP7 card was designed before Virtex-7 Engineering Silicon was available and so a lot of design work relied on preliminary documentation and discussion with Xilinx engineers. The MP7 card was, therefore, the first card in the CMS experiment to use Xilinx 7-series FPGAs. The experience of designing for and powering the Virtex-7 are discussed, along with lessons learned. The challenges associated with cooling an FPGA dissipating of-the-order 40W is also discussed.

Upgrade of the Muon Sorter in the Cathode Strip Chamber Level 1 Trigger System at CMS

The top level of the Level 1 Trigger System in theCathode Strip Chamber (CSC) detector at CMS consists of the Track Finder(TF) crate with 12 Sector Processors (SP) and one Muon Sorter (MS) board.The MS provides sorting of up to 36 trigger objects from the SP boards,selects the four best (by a definable criterion) ones, and transmits then tothe Global Trigger crate of CMS. With the anticipated LHC luminosityincrease above 1034 cm−2s−1 at an energy of 6.5–7 TeV/beam theCSC TF needs to be upgraded. The new CSCTF will be robust to higheroccupancies, provide improved transverse momentum assignment and increasedprecision of the muon output variables. A transition from the current 9U VMEelectronic standard to the more flexible uTCA and utilization of the XilinxVirtex-6 and Virtex-7 FPGAs, with multiple embedded gigabit links, willallow us to build a higher performance TF such that the MS functions can beperformed by one of the SP modules. We present here the results of ourefforts in the past year to upgrade the CSC Muon Sorter, including the shortterm modifications of the existing VME board, long-term transition to theuTCA as well as firmware development for both of these projects.

Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM Technique

In this paper, we present a new multi-tone test signal generation method with different frequency tones uniformly distributed across a wideband spectrum. It employs OFDM (orthogonal frequency-division multiplexing) spread spectrum technique to allow users to define signal parameters with a great flexibility as per the test requirements. This OFDM method essentially starts from the frequency sampling and then conversion to generate time domain signals, which can significantly reduce the number of data points in the signal generation. Response of such test signals from the device under test (DUT) can be captured and analyzed so as to characterize frequency response associated with each frequency tone. For validation, simulations with Matlab Simulink tool and hardware implementation on a Xilinx Virtex5 FPGA board are developed.

The Readout Electronics of the Micromegas-Based Large Time Projection Chamber Prototype for the International Linear Collider

This work presents the design, implementation and test of prototype modules of a Time Projection Chamber based on Micromegas amplification technology which was built in view of the future International Linear Collider. The main goals of this development are to investigate the performance of the detector and to demonstrate the feasibility of extremely compact and low power readout electronics. We based the front-end electronics on the AFTER chip, a 72-channel ASIC originally built for the T2K experiment, and integrated it with new hardware, mechanics and cooling to read out the 1728 channels of a detector module while staying confined in the available area of ~ 220 cm2. The digital part of a module is based on a Xilinx Virtex-5 FPGA which interfaces to the 24 AFTER chips used for the readout. We present the operation of a vertical slice of the complete detector and readout system. In particular, our tests show that the resistive anode of the Micromegas detector, which is primarily designed to improve tracking resolution, allows operation without the spark protection circuit normally required on each readout channel.

A Stepped-Up Tree Encoder for the 10-ps Wave Union TDC

A stepped-up tree encoder (SUTE) has been designed to deal with the issue of non-thermometer-to-binary (NTH2B) encoding for a 10-ps wave union FPGA TDC. The encoder is made up of two pipeline stages: pre-encoding and parallel encoding, and is capable of bubble error correction (BEC) as well. With this encoding algorithm applied in a Xilinx Virtex-4 FPGA, we achieved a NTH2B conversion rate of up to 100 MHz for more than 200-bit non-thermometer codes.

Recomputing with Permuted Operands: A Concurrent Error Detection Approach

Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%-27.3%, and the throughput is 1.2-23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities.

A Low Power Design of Single Precision Floating Point Multiplier for Computing Techniques

A design and implementation of a 32 bit fast floating point multiplier with the single precision IEEE 754-2008 standard target for Xilinx virtex-5 FPGA. The proposed design and timing information of the multiplier sub-module has been calculated and the proposed design intends to increase the speed on the multiplier by reducing delay at every stage using optimal adder design. The proposed multiplier is made to multiply two floating point numbers and generate the output to make minimum time delay. The modules have been written in verilog HDL and it is simulated using the Xilinx ISE12.1 targeted on the FPGA.

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design

The goal of this work is to develop a methodical approach for analytical soft error sensitivity analysis in SRAM-based FPGAs. Compared to other non-destructive techniques, the proposed approach can be applied very early in a design flow. This is achieved by extracting information about an application under development from high level models (e.g. C/C++ descriptions or Matlab Simulink models) and then invoking pre-established libraries where other information related to soft error sensitivity of primitive components are stored beforehand. Our library-based approach is validated by comparing our early estimation results to those obtained through synthesis, placement and routing of complete designs, for two different ways of estimating the number of potentially critical configuration bits. We first explore two different design architectures for implementing Finite Impulse Response filters. The design architectures are explored under two different implementation options, for a Xilinx Virtex-5 FPGA: LUT based and DSP48E block based. Then we apply our estimation technique on a more complex design. namely a GMSK demodulator. Results show that the worst case relative error, caused by our estimation technique with respect to the results obtained after synthesis, placement and routing is 7,2 %, and in most cases, it is less than 5 %. Mean time between failures are provided for the different design architecture and implementation options, to illustrate how our technique can help designers make early choices to build more reliable designs without performing the whole implementation, as our early estimation results are close to those obtained later in the design process.

Design and Implementation of a Multi-DSP Processing System

A multi-DSP real time image processing system is designed, with TI's TMS320C6455 as core processor as well as Xilinx Virtex5 FPGA for pre-processing and important data channel. The system has completed testing verification and results show that the design is feasible and reliable.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human–computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.