Abstract
When the LHC resumes operation in 2015, the higher centre-of-mass energy and high-luminosity conditions will require significantly more sophisticated algorithms to select interesting physics events within the readout bandwidth limitations. The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps. The upgrade will improve the energy and position resolution of physics objects, enable much improved isolation criteria to be applied to electron and tau objects and facilitate pile-up subtraction to mitigate the effect of the increased number of interactions occurring in each bunch crossing. The design of the upgraded system is summarised with particular emphasis placed on the results of prototype testing and the experience gained which is of general application to the design of such systems.
Highlights
The LHC will restart in 2015 with a higher centre-of-mass energy and luminosity
The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps
The upgrade will improve the energy and position resolution of physics objects, enable much improved isolation criteria to be applied to electron and tau objects and facilitate pile-up subtraction to mitigate the effect of the increased number of interactions occurring in each bunch crossing
Summary
The LHC will restart in 2015 with a higher centre-of-mass energy and luminosity. To allow the CMS physics programme to fully exploit these increases the CMS Level-1 trigger must maintain similar efficiencies for searches and precision measurements to those achieved in 2012. The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps. 2. Hardware Three boards, shown, are required to modify the existing trigger: the oSLB, the oRM and the oRSC.
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