Abstract
To provide an optimised implementation aimed at calculating the chirp scaling (CS) coefficients used in state-of-the-art spaceborne synthetic aperture radar (SAR) imaging systems. Built on the core concept of breaking down the CS coefficient calculation into basic operations, we propose a new architecture that adopts a dual-operator engine as the basic processing unit and seeks to optimise the switching network of operator engines through an appropriately interconnected grouping of various calculations. A wide variety of SAR imaging architectures based on fast Fourier transformation-CS operations may benefit from this work. The proposed architecture is implemented in a Xilinx Virtex-7 FPGA process; a comparison between test results and results obtained from an off-the-shelf counterpart confirms the efficacy of the proposed architecture.
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