Xilinx ISE Research Articles

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

SummaryA design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation based scalable rounding approximate multiplier (APM‐CDF‐ESDCSA‐TOSAM) is proposed in this article for image processing application. The proposed ESDCSA‐TOSAM is used to speed up the filter design with less area and less power consumption. In the existing designs, a carry select adder was used that was a rapid binary adders, even though, it consumes maximal area and power. For that reason, lower power, area efficient with higher speed eminent speed dual carry select adder (ESDCSA) is used in this work. The proposed ESDCSA is a fastest binary adder, which consumes less power and area. To design the ESDCSA, three blocks are used: half sum with carry generator (HSCG), final carry generator (FCG), final sum generator (FSG), these are reducing the power and area. TOSAM is used to reduce more partial products by truncating each input operands depending on its leading one‐bit position. The proposed filter is designed on Xilinx ISE 14.5 design tools. The experimental performance of the proposed filter attains lower delay 59.61%, 37.91%, 34.99%, 28.09%, 44.04% and 38.23% compared with existing filters.

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. “Advanced error recovery for parallel systems,” the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.

Real Time Implementation of Biometric-based EVM System for Distinct Verification

In current existences, many techniques have been developed to cast votes. The existing scenario is tremendously aiming towards the development of an efficient voting system, which ensures individual authentication and reduces malpractices. It is a challenging perspective to recognize each and every individual person casting the vote. The proposed work considers this scenario and developed a controller based electronic voting machine using R305 Fingerprint sensor for biometric authentication of every individual. The controlled electronic voting machine gives ample scope to cast the votes in simpler manner without minimizing the efficient results. The proposed digital Biometric-based EVM is presented in this work. The processed flow for creating this biometric based EVM is implemented on FPGA board using Verilog software on Xilinx ISE. The experimental results produce efficient verification of unique authentication on selections of political parties.

Design and Implementation of Area Efficient 16-bit Carry Skip Adder

Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area and delay are analyzed using Xilinx ISE 14.7. The hardware simulation is done in Xilinx Spartan 3E FPGA.

Efficient transmission of FECG signal using MIMO – OFDM

The extraction of Fetal Electrocardiogram (FECG) during labor or prenatal phases of pregnancy holds significant importance for early prediction of heart abnormalities. The accuracy of the extracted FECG is crucial for effective diagnosis, but the presence of external noises, particularly from the Maternal ECG (MECG), poses a major challenge in obtaining precise information. To address this issue in biomedical data processing, the study employs Finite Impulse Response (FIR) filters using an array multiplier. One notable challenge encountered in this process is the interference caused by external noises, leading to higher delay and power dissipation. In response, a modified High-Performance Multiplier (HPM) based modified booth multiplier is thoroughly reviewed and validated. This modification aims to enhance overall performance and enable high-speed operations in filtering the FECG signals. The effectiveness of these modified multipliers is assessed using ECG signal information collected from the MIT-BIH Arrhythmia Database, comprising 120 samples. In addition to noise filtering, the study explores the validation of Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) transceivers. These transceivers play a crucial role in ensuring the effective transmission of the extracted FECG signals. The research reveals a significant reduction, up to 80.4%, in both area and power dissipation during simulations conducted in Xilinx ISE 9.1 and Cadence Virtuoso. This achievement highlights the potential for improved efficiency and reliability in the processing and transmission of FECG signals, paving the way for advancements in early detection of fetal heart abnormalities.

Development of a 4-digit BCD multiplier architecture with similarity investigator

Arithmetic Logic Units (ALUs) are very important components in computer systems. They are digital circuits utilized to perform a wide variety of arithmetic and logic operations. Modern Central Processing Units (CPUs) contain powerful and complex ALUs. One such operation performed by ALUs is that of Multiplication. Multiplication scales one variable by another. This research involves the design, implementation and verification of a 4-digit BCD Multiplier Core with Similarity Investigator for path delay reduction. The system is implemented using Xilinx ISE 14.7, verified using ISim and Digilent Nexy3 toolkit and was utilized as the development platform. The research concluded that similarity investigation was capable of path delay reduction of up to 97% compared to that when no similarity investigation was applied. The system can conduct a maximum of 889 unique multiplication operations before facing diminishing returns as a result of the similarity investigation search procedure.

A Review of Vedic Mathematics for the Design of High-Speed Arithmetic RISC Processors

Vedic Mathematics is a collection of techniques and concepts developed from ancient Indian mathematical books known as the Vedas. These strategies are designed to make different mathematical computations easier and faster. High-throughput RISC Processor Design, on the other hand, includes the creation of processors that prioritize the execution of a high number of instructions per unit of time. If there have been breakthroughs relating to Vedic Mathematics and High-Throughput RISC Processor Design, it would be intriguing to investigate how these old mathematical ideas may be utilized to improve the efficiency of current processor designs. Give a summary of the work, stressing the potential benefits and drawbacks of incorporating Vedic Mathematics concepts into the design of High-Throughput RISC computers. Introduce Vedic Mathematics and High-Throughput RISC Processor Design separately. Explain briefly why you're looking at incorporating Vedic Mathematics into CPU architecture. Outline key Vedic Mathematics concepts that may be applied to processor design. What distinguishes these ideas from typical mathematical approaches Provide an overview of the fundamental ideas and issues involved in the design of high-throughput RISC processors. Emphasize the critical areas for improvement and integrating principles from Vedic Mathematics into Processor Architecture: Investigate the use of Vedic Mathematics principles in processor architecture to discuss how these concepts may be utilized to solve specific problems or improve aspects of high-throughput RISC architectures. The importance of multipliers in Arithmetic Unit performance is underlined. The incorporation of Vedic Science, an ancient mathematical system comprised of 16 Sutras, implies a fresh method for arithmetic computations. The suggestion comprises optimizing the Vedic multiplier type Urdhva Triyakbhyam by substituting Convey Save Viper for the usual carry. This is done to reduce delays caused by standard adders and incomplete products aspire to outperform traditional designs in terms of speed. The explicit data on the speed gains is obtained and how they were assessed will bolster the claims and utilization of the proposed proficient Vedic multiplier in the number juggling module of the RISC processor. In addition, stating its application in the field of digital signal processing (DSP) broadens the scope of work. Validation of RTLs and FPGAs for the Register-Transfer Level (RTL) implementation of the proposed Math Unit in VHDL, paired with simulation using Xilinx ISE EDA tools, is a useful step in verifying the design. Validation on an FPGA device, especially a Vertex-IV, provides credibility to the suggested solution.

FPGA Tabanlı LogSig ve TanSig Transfer Fonksiyonlarının IQ-Math Sayı Standardında Tasarımı ve Gerçeklenmesi

Yapay Sinir Ağları (YSA), günümüzde sinyal işleme, optimizasyon, tahmin, karar verme ve kontrol gibi bir çok mühendislik alanında yoğun şekilde kullanılmaktadır. YSA yapılarının çalışmasını doğrudan etkileyen önemli bölümlerinden birisi de Transfer Fonksiyonlarıdır (TF). Doğrusal olmayan TF tasarımlarının gerçek zamanlı tasarımı üstel fonksiyon içerdiğinden oldukça zor bir şekilde gerçekleştirilmektedir. Bu çalışmanın ilk aşamasında, literatürdeki çalışmalardan farklı olarak doğrusal olmayan Logaritmik Sigmoid (LogSig) ve Tanjant Sigmoid (TanSig) TF, 32-bit (16I-16Q) IQ-Math formatında VHDL dilinde tasarlanmıştır. İkinci aşamada, VHDL dilinde FPGA çiplerinde çalışmak üzere örnek bir üç giriş-üç çıkışlı bir YSA (ileri beslemeli) yapısı 32-bit IQ-Math formatında modellenmiştir. Tasarımın gizli katmanında 8 adet nöron, gizli katmanda LogSig ile TanSig TF ve çıkış katmanında ise PureLin TF kullanılmıştır. Örnek YSA tasarımı iki farklı TF tasarımı için ayrı bir testbench dosyası oluşturulmuş ve bu tasarımlar VHDL ile Xilinx ISE DS programı ile test edilmiştir. Elde edilen simülasyon sonuçlarına göre nümerik tabanlı LogSig ve TanSig TF içeren YSA tasarımları için MSE ve RMSE hata analizleri yapılarak sonuçlar sunulmuştur. Ardından her bir tasarım XC7K70T-3FBG676 FPGA (Kintex-7) için sentezlenerek Place-Route prosesi gerçekleştirilmiştir. Place-Route prosesinden elde edilen FPGA çip kaynak kullanımı istatistikleri sunulmuştur. Tasarımlara ait hata analizi sonuçlarına göre YSA-LS (LogSig-tabanlı YSA) tasarımı 8.86E-06 MSE ve YSA-TS (TanSig-tabanlı YSA) tasarımı 7.92E-02 MSE sonuçları elde edilmiştir. Bu çalışmadan elde edilen sonuçlar ile IQ-Math tabanlı LogSig ve TanSig aktivasyon fonksiyonu tasarımlarının gerçek zamanlı YSA uygulamalarında güvenli bir şekilde kullanılabileceği gösterilmiştir.

Design of Vending Machine using FPGA

The vending machine is an automated device that dispenses a variety of products to customers when cash or a credit card is placed, including food, beverages, newspapers, tickets, and more. Contrary to traditional purchase methods, vending machines are more convenient and available. Today, the market for vending machines generates enormous annual revenues for developed countries like the United States, Japan, China, and some other Asian nations, including India. The goal of the paper is to create a vending machine that can dispense three different items at varying costs with the added functionality of "return change" when a coin of a higher denomination is input and "return money" when a request is cancelled. Coins of the values of five and ten are accepted by the machine. The design of vending machines uses the finite state machine (FSM) methodology. The design is accomplished by using behavioural modelling to create the Verilog code for the FSM-based machine and the Xilinx ISE tool to simulate the test-bench for three items.

Моделирование функционального узла управления матричным индикатором на базе программируемой логической интегральной схемы

The article presents the process of simulation of the functional control unit of a matrix indicator on the basis of a programmable logic integrated circuit in the Xilinx Vivado Design Suite tool programming environment. Analysis and synthesis of the hardware language constructs, as well as developing RTL models were carried out using the Xilinx ISE software. There have been defined the functional modules common to the matrix indicator control unit: 
 a finite state machine that generates a sequence of characters; a matrix indicator control unit that outputs a sequence 
 of characters to a matrix indicator generating a finite automaton; a button bounce filter; frequency divider. A logic unit model combining functional nodes has been realized. Xilinx ISE CAD produced an RTL model that shows interaction of the nodes and the appearance of the top level. The matrix indicator control unit is presented as four interrelated devices: a column counter that enumerates the columns; a column decoder that takes input values and produces the value "1" only to one of the outputs, the number of which is equal to the number of the column whose value is put to the input; a character code register which receives, stores and transmits character codes; read-only memory which stores encodings of lines for sending an information signal in case of arrival of a particular word or a column. The specific features of implementing the modules on programmable logic are considered. A test module developed in the Verilog language was designed for verification, which is a step-by-step input of values and delays between input. Testing the modules that make up the matrix indicator control unit was carried out.

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

Design of Digital FIR Filter with Systolic Architecture using Reversible Logic Gates

The design of Digital filters plays a prominent role in the present scenario. The delay and area are the two major components that need to be concentrated on. The delay tap present in FIR filters should be suppressed to inflate the speed of the system. In this paper, the FIR filter design using systolic architecture with associative technique is implemented. This system includes a number of identical elements that are interconnected one after another by programmed manner to get the specified output. Here the proposed systolic FIR is compared with TDA logic block using bisection technique. There will be a greater reduce of critical path using the systolic architecture. To intensify the speed and to truncate the system delay the processing elements such as adders, multipliers and delay elements are designed by reversible logic operations. The proposed filter is better in many aspects such as density of gates, power consumption and delay outputs compared with existing filter. Experimental results are performed using the Xilinx ISE tool.

CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System

This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are 821.92 Mbits/s and 520.768 Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications.

Signature based Merkle Hash Multiplication algorithm to secure the communication in IoT devices

Great extent of modernization in intelligent device automation and wireless sensor network have encouraged the augmentation of IoTs to interconnect millions of actual devices to the Internet with the help of sensors, actuators and communication technologies. IoT devices with the potential of pervasive sensing and quantifying ability, it becomes an essential segment of the future Internet. The sixth generation (6G) enabled IoT networks are predicted to transform the data sharing and communication for a future of thorough brilliant and sovereign systems. However, secure communication in a sensor network is very difficult and is more amplified by the use of latest 6G IoT technology which is vulnerable to different kinds of attacks due to their limited security features. Existing security systems like RSA and Elliptic curve cryptography which is based on large integer factors and the discrete logarithmic problem is vulnerable to the attack which emerges from quantum computers. The computing capacity of a quantum computer is higher than classical computers. A 30-qubit quantum computer has the equivalent computing capacity as a traditional silicon-based computer computes at 10 teraflops per second. To secure the communication in the present and future IoT network, an enhanced Hash-based Post-Quantum Cryptography (PQC) architecture named Signature-based Merkle Hash Multiplication (SMHM) algorithm is proposed. In the proposed scheme, the Hash-based Merkle signature algorithm is enhanced using the Bernoulli Karatsuba Multiplication algorithm to secure the data storage and communication in IoT devices. The FPGA based proposed model is implemented in the Xilinx ISE14.5 simulator, both Hardware Descriptive Language (HDL) and High-Level Synthesis (HLS) approach is used to calculate the performance metrics which improved 33% frequency, 22% area, power consumption up to 13%, 10% error and 15% delay.

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

128-Bit LEA Block Encryption Architecture to Improve the Security of IoT Systems with Limited Resources and Area

The LEA block encryption algorithm is an architecture suitable for IoT systems with limited resources and space. It was developed by the National Security Technology Research Institute in 2013 and established as an international standard for cryptography by the International Electrotechnical Commission in 2019, drawing much attention from developers. In this paper, the 128-bit LEA block encryption algorithm was light weighted and implemented in a hardware environment. All modules share and reuse registers and are designed and implemented in a bottom area through the resource sharing function. As a result of synthesis using Xilinx ISE 14.7 Virtex-5 as a design environment, the maximum frequency achieved 190.88 MHz and has a processing speed of up to 128 Mbps. Compared to the previously designed architecture, we present a bottom-level hardware design with a 128-bit LEA algorithm implemented with a 49.8% reduction in Flip-Flop, 18.8% reduction in LUTs, and 67.6% reduction in Slices.

Identification of characteristics frequency and hot-spots in protein sequence of COVID-19 disease

COVID-19 has threatened the whole world since December 2019 and has also infected millions of people around the globe. It has been transmitted through the SARS CoV-2 virus. Various proteins of the SARS CoV-2 virus have an important role in its interaction with human cells. Specifically, the interaction of S-protein with human ACE-2 protein helps in entering of SARS CoV-2 virus into a human cell. This interaction take-place at some specific amino-acid locations called as hot-spots. Understanding of this interaction is helpful for drug designing and vaccine development for new variants of COVID-19 disease. An attempt has been made in this paper for understanding this interaction by finding the characteristics frequency of SARS-related protein families using the resonance recognition model (RRM). Hardware implementation of Bandpass notch (BPN) lattice IIR filter system architecture is also carried out, which is used for hot-spots identification in SARS CoV-2 proteins. Various signal processing techniques like retiming, pipelining, etc. are explored for performance improvement. Synthesis of proposed BPN filter system has been done using Xilinx ISE EDA tool on Zynq-series (Zybo-board) FPGA family. It is found that retimed and pipelined architecture of hardware-implemented BPN lattice IIR filter-based hot-spots detection system improves the speed (computational time) by 14 to 31 times for different SARS CoV2 related proteins as compared to its MATLAB simulation with similar functionality.

MODIFIED HIGH SPEED AND LOW POWER 32-BIT VEDIC MULTIPLIER DESIGN AND IMPLEMENTATION

–The multiplier speed is a significant feature as the multiplier forms an important part of many systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system hence it is the speed determining factor of the system. An improvement in speed of the multiplier leads to an improvement in speed of the overall speed. The multiplier speed not only depends on the multiplication technique used it is also depends on the type of adder employed for the addition of the partial products. The proposedhigh speed and low power 32-bit Vedic multiplier architectures based on Vedic sutra namely, Urdhva-Triyag using Carry Save Adder(CSA) has been implemented.Among various methods of multiplication, recently Vedic multipliers are being more efficient. These sutras meant for fastercalculation.Urdhva-Triyag is more efficient than other multipliers with respect to speed. The most significant aspect of the Urdhva-Triyag sutra is, the developed multiplier generates allpartial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further.Finally, the results are comparedwith conventional multipliers to show the efficiency in terms of speed.The effectiveness of theproposed method is synthesized and simulated using Xilinx tool using Verilog coding Software Tools:  Xilinx ISE 14.7 Tool Key Words:Vedic Multiplier, Urdhva-Triyagbhyam sutra, Ripple Carry Adder,Carry Save Adder.

Half diagonal matrix codes for reliable embedded memories

Reliability of embedded memories is dependent on at-speed rated correction capability of error detection and correction codes. Many critical applications like medical databases, rocket launch details stored in memories require accurate data and which cause major human losses or economy losses even if a 1% of data is compromised. This paper focuses on developing improved reliable error detection and correction codes with minimum redundant bits and maximum code rate. The decoder uses the concept of Encoder Reuse Technique along with the Modulo-2 addition to calculate syndrome, error location and correction of data bits when data is read from memory. The codes are represented in verilog hardware description language and simulated in the Tool Xilinx ISE 14.5 for XC7Z020-1CLG484 FPGA. The codes are evaluated for their performance in terms of technology parameters like area, delay, power, power – delay product, etc. Also for other parameters like bit overhead, code rate, code efficiency, correction coverage, correction efficiency, etc and correction coverage per cost for combined evaluation. The implemented half diagonal code is more effective as compared to existing matrix codes, it reduces bit overhead at least by 5.5% to 46.96% and coding rate increased at least by 16.74% to 23.85%.