Abstract

The LEA block encryption algorithm is an architecture suitable for IoT systems with limited resources and space. It was developed by the National Security Technology Research Institute in 2013 and established as an international standard for cryptography by the International Electrotechnical Commission in 2019, drawing much attention from developers. In this paper, the 128-bit LEA block encryption algorithm was light weighted and implemented in a hardware environment. All modules share and reuse registers and are designed and implemented in a bottom area through the resource sharing function. As a result of synthesis using Xilinx ISE 14.7 Virtex-5 as a design environment, the maximum frequency achieved 190.88 MHz and has a processing speed of up to 128 Mbps. Compared to the previously designed architecture, we present a bottom-level hardware design with a 128-bit LEA algorithm implemented with a 49.8% reduction in Flip-Flop, 18.8% reduction in LUTs, and 67.6% reduction in Slices.

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