Design of Digital FIR Filter with Systolic Architecture using Reversible Logic Gates

Abstract

The design of Digital filters plays a prominent role in the present scenario. The delay and area are the two major components that need to be concentrated on. The delay tap present in FIR filters should be suppressed to inflate the speed of the system. In this paper, the FIR filter design using systolic architecture with associative technique is implemented. This system includes a number of identical elements that are interconnected one after another by programmed manner to get the specified output. Here the proposed systolic FIR is compared with TDA logic block using bisection technique. There will be a greater reduce of critical path using the systolic architecture. To intensify the speed and to truncate the system delay the processing elements such as adders, multipliers and delay elements are designed by reversible logic operations. The proposed filter is better in many aspects such as density of gates, power consumption and delay outputs compared with existing filter. Experimental results are performed using the Xilinx ISE tool.