Xilinx Field Programmable Gate Array Research Articles

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA

The offloading and acceleration of database operations on field programmable gate arrays (FPGAs) have been extensively studied for a long time. Architectures of join, a key database operation, have been proposed and optimized on FPGAs. However, these join architectures are either resource-intensive or have low-throughput. In this brief, we focus on the equi-join and propose a resource-efficient join architecture based on a tree model. The architecture needs two phases: the build phase, in which a binary tree is built by using the first database table, and the probe phase, in which the architecture searches the tree to find matching solutions through a second database table. In addition, we propose a parallel implementation for this architecture to improve its performance. The proposed design was implemented on a Xilinx FPGA, and the results were compared with the most recent works on hardware join. The experimental results demonstrate that for a range of parallelism and dataset sizes, our design achieves a data throughput of 8–100 million tuples per second, which is compatible with the bus rate, and performs well in balancing resource utilization and data throughput.

A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core

Cryptographic cores integrated with self-test ability fulfill both data security and reliability requirements of the Internet of Things (IoT) network. However, from the IoT perspective where most devices are resource constrained, a fundamental problem associated with most of the self-test architectures is high hardware overhead due to the additional circuit for self-test operation. This paper presents the design of a low-cost self-test architecture and its integration with the PRESENT cipher core. The hardware overhead of the proposed low-cost self-test architecture is reduced by adopting two key strategies: 1) using hardware-efficient X-Compactor technique for test response compaction and 2) reusing the PRESENT cipher core as a Test Pattern Generator (TPG). The proposed self-test architecture is implemented on different Xilinx Field Programmable Gate Array (FPGA) platforms and devices. Analysis of the implementation results shows that the proposed self-test method occupies 23% less hardware area overhead and provides 14% higher throughput per slice performance with the fault coverage of over 99% compared with the existing self-test designs. The resulting analysis indicates that the proposed self-test design is one of the most viable testing solutions for resource-constrained IoT devices.

Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters

Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel counters (GPCs) were synthesized on FPGAs to address this issue. Despite the improved timing performance of GPC-based compressor trees, area reduction is not as significant as delay, and can be further optimized. In this paper, we propose improved GPC mappings as well as new approaches for GPC cascading and binding for Xilinx FPGAs. With these improvements, we develop an integer linear programming (ILP) method for FPGA synthesis of GPC-based compressor trees that supports cascading and binding between GPCs. Experimental results show that the single-cycle compressor trees produced by the proposed ILP can reduce the average area by 42.40% compared with those generated by existing heuristic method, but are 13.16% slower; the pipelined compressor trees produced by the proposed ILP can reduce the average area by 33.43% at the cost of an average 14.35% decrease in maximum clock frequency compared with those obtained by existing heuristic method.

A Low-Cost Design of 2D Median Filter

The median filter plays an important role in image processing for noise removing. To enhance the operating speed, hardware implementation of median filter on field programmable gate arrays (FPGA) or application specific IC (ASIC) are necessary and inevitable. This paper presents a low-cost and high-throughput hardware design for two-dimensional (2D) median filter. Two techniques are employed to reduce circuit area. One is the parallel three-valued sorting method for reducing the number of pipelined registers under constant speed, and the other is the functional sharing method used to implement median value sorting with the least number of comparisons. The proposed 2D median filter is implemented by two different synthesized methods. One is synthesized by Synopsys Design Compiler with the TSMC 90nm cell library (ASIC design) and the other is synthesized by Xilinx FPGA Virtex7 XC7VX690T (FPGA design). Experimental results show that the area cost of the proposed design is reduced more than 30% on average in comparison to the previous designs.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction

This paper presents an all-digital time-domain smart temperature sensor (TDSTS) with a cost-efficient curvature correction, which can effectively improve the accuracy and cost. Inverter-based TDSTSs are low cost and low complexity but they exhibit a significant curvature, which severely impairs their accuracy. Linearity enhancement through linear interpolation reduces the curvature and results in a twofold improvement in the accuracy. In this paper, the proposed curvature correction not only simplified the scheme to reduce the hardware cost but also successfully eliminated the curvature to achieve the most suitable accuracy. In addition, the correction procedure was also simplified. The TDSTS was implemented in eight Xilinx field-programmable gate arrays for performance verification and occupied 74 slices per sensor. The logic utilization for the proposed curvature-corrected circuit was 17 slices, and its cost was only 23% of the hardware cost. The experimental results indicated that the maximum inaccuracy decreased from 5 °C to 1.8 °C over the temperature range of −20 °C–100 °C, resulting in an approximate threefold improvement in the accuracy. Compared with a previous study, the improvements of 30% and 43% in the accuracy and cost, respectively, successfully validate the proposed technique.

Control with high performances based DTC strategy: FPGA implementation and experimental validation

ABSTRACTThis paper aims to improve the induction motor performances using a modified Direct Torque Control (DTC). The DTC is featured by its simple structure and fast dynamic response. Also, it does not require a speed sensor and it is less dependent on the motor parameters. However, the basic handicaps of this method are the torque ripples and the current distortions due to the presence of the hysteresis controllers. This paper aims; firstly, to replace the hysteresis controllers and the switching table by a fuzzy logic system in order to overcome these handicaps. Furthermore, the sampling frequency is another parameter which must be investigated to reduce the commutation losses and the harmonic stator current waves. The second purpose of this paper is to reduce the execution time using a Field Programmable Gate Array (FPGA). The FPGA is able to execute the Fuzzy DTC (FDTC) with a higher sampling frequency, thanks to its parallel processing relative to the Digital Signal Processor (DSP). The FDTC model is verified by simulation using system generator tool and validated by experimentation utilizing an FPGA Virtex 5. Thus, excellent performances at low processing time are obtained using the Xilinx FPGA Virtex 5.

Adaptive direct power control based on ANN-GWO for grid interactive renewable energy systems with an improved synchronization technique

This paper investigates the improvement of synchronization technique for single-phase inverter. Specifically, the paper proposes a modified structure of second-order generalized integrator with frequency-locked loop (SOGI-FLL) with FLL gain normalization. The proposed structure enhances the frequency detection, which makes it a powerful technique under distorted grid voltage. The validation of the proposed synchronization method includes simulations and experimental tests using Xilinx field programmable gate array (FPGA) as the target device. Moreover, time domain simulations using the direct power control (DPC) with the proposed structure are performed. The decoupled active and reactive powers are controlled using the artificial neural networks (ANNs) trained by the mean of a metaheuristic algorithm. In this paper, the grey wolf optimizer (GWO) is proposed to train the multilayer perceptron (MLP). The proposed approach shows better generation of synchronization signals and smooth power quality, making it suitable for grid-tied and microgrids (MGs) power systems control.

An FPGA-Based Implementation of a Multifunction Environment Sensing Device for Shared Access With Rotating Radars

To protect radar receivers and to facilitate shared access in radar bands, regulatory bodies have recommended the use of spectrum monitoring devices called environmental sensing capability (ESC). High-speed and low-cost ESC devices are required to process in real time the large amount of data (in-phase and quadrature samples) for the detection of radar signals and to differentiate them from secondary users (SUs) signals. In this paper, we present a field-programmable gate array (FPGA)-based design and implementation of a multifunction ESC device that can detect radar pulses and can also differentiate them from SU signals in microsecond time scales. The proposed ESC device performs the following tasks in parallel: 1) it detects and differentiates between radar and SU signals; 2) it measures received signal strength from SUs for radar protection; and 3) it also measures SUs’ airtime utilization (ATU) in a channel, which can be used to perform load balancing (based on ATU) of SUs on different channels for efficient access. Detection of signals requires threshold setting. We present a novel minimum-based threshold setting technique, which is suitable for real-time operation of energy detectors. We implement a prototype of the proposed ESC device design on a Wireless Open-Access Research Platform node, which is equipped with a Xilinx FPGA. We evaluate the performance of the implemented device and show that with very high probability (close to 100%), it detects and differentiates between radar and SU signals. Moreover, it also accurately measures the ATU of SUs.

Design and Realization of Controller for Static Switch in Microgrid Using Wavelet-Based TSK Reasoning

A microgrid may comprise several zones with local loads and distributed generation resources. If a fault occurs in a zone, then a static switch between the faulty and fault-free zones must be activated to detect/classify the faults and enable the breaker to open the circuit immediately. This paper presents a new method for designing a detection/classification module in a static switch using the Park Transform (PT), Multiresolution Analysis (MRA) and Takagi–Sugeno–Kang (TSK) fuzzy rules. Both wavelet coefficients/energies of the d -axis component, within 0.96–1.92 kHz, obtained by MRA and PT are employed to effectively detect and classify the fault types using the local fault signals near the static switch without a complicated communication system. The proposed TSK fuzzy rules, defined by the scenario data only, successfully classify the faults. The proposed method is verified by hardware-in-the-loop simulation using a real-time digital simulator and a realistic 5 kVA static switch. The proposed method is implemented in a Xilinx field-programmable gate array. Test results show that the proposed method is efficient in the real-time control environment of a microgrid.

Configuration Self-Repair in Xilinx FPGAs

The usage of static random access memory-based field programmable gate arrays (FPGAs) on high-energy physics detectors is mostly limited by the sensitivity of devices to radiation-induced upsets in their configuration. In this paper, we describe a scrubber core designed for Xilinx FPGAs, based on configuration redundancy. When no upsets happen in homologous redundant bits and the scrubber is functional, the adopted redundancy makes it possible to correct all the errors. In fact, the scrubber corrects its own configuration and the one pertaining to a given user design. We discuss the architecture and two implementations of the scrubber, corresponding to different flavors of triple modular redundancy. We report results from proton irradiation tests, which prove that our core can extend the lifetime of a benchmark circuit up to 290%.

Cloud Based Remote FPGA Lab Platform: An Application of Internet of Things

IoT (Internet of Things) is the next generation of the Internet. The main goal of IoT is to connect each and every physical object to the Internet Cloud. This concept is introduced by bringing IoT technology to the laboratories, making expensive laboratory equipment available on-cloud for real-time experimentation. In this paper, an on CLP (Cloud Laboratory Platform) is presented by employing the concept of IoT to the academic experimentation environment. The CLP allows a rapid deployment of an online laboratory system enabling students and researchers to perform actual experiments on the on-Cloud laboratory equipment using a web interface. A web interface for end users to access front end of the system. This interface was developed for login purposes so that any user can perform experiments from anywhere. The interface also provides options for comments and feedback. Moreover, this research contribution also facilitate users to test their designs and record observations in real-time on the equipment. For demonstration purposes, a remote lab has been developed for high-tech Xilinx FPGA (Field Programmable Gate Array) development boards, namely Spartan-II and Spartan-III. This project aims to provide students a new tool to enhance their learning experience and encourage them to test their theoretical knowledge in practical applications.

A generic TC-based method to find the weakness in different phases of masking schemes

Masking is one of the most commonly used Side-Channel Attack (SCA) countermeasures and is built on a security framework, such as the ISW framework, and ensures theoretical security through secret sharing. Unfortunately, the theoretical security cannot guarantee practical security, because several possible weaknesses may exist in the actual implementation. These weaknesses likely come from the masking schemes or are introduced by the implementation methods. Finding the possible weakness of the masking scheme is an interesting and important issue for real applications. In this paper, the possible weaknesses for masking schemes in Field-Programmable Gate Array (FPGA) design are discussed. It was found that the combinational circuit is the key to the security of masking schemes. The Toggle Count (TC) method and its extension are utilized to evaluate the security of masking schemes in the design phase and the implementation phase separately. Comparing different logic-level simulators for the Xilinx FPGA platform, the behavioral and post-translate simulations are considered as the analysis method in the design phase, while the post-map and the post-route simulations are used to find the weakness during the implementation phase. Moreover, a Standard Delay Format (SDF) based improvement scheme is proposed to significantly increase the effectiveness of the TC model.

FPGA implementation and control of chaotic systems involving the variable-order fractional operator with Mittag–Leffler law

This paper presents the simulation and control implementation on a Field Programmable Gate Array (FPGA) for a class of variable-order fractional chaotic systems by using sliding mode control strategy. Four different fractional variable-order chaotic systems via Atangana–Baleanu–Caputo fractional-order derivative were considered; Dadras, Aizawa, Thomas and 4 Wings attractors. A methodology has been developed to construct variable-order fractional chaotic systems using LabVIEW® software for its implementation in the National Instruments myRio-1900 (Xilinx FPGA Z-7010)® device. The variable-order fractional differential equations and the control law were solved using the variable-order Adams algorithm. Finally, simulation results show that FPGA provides high-speed realizations with the desired accuracy and demonstrate the effectiveness of the proposed sliding mode control.

Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions

This paper presents a methodology for digital switching noise suppressions on the power lines at a fundamental frequency as well as its harmonics by using a clock scheduling technique in the frequency domain. Our approach provides a deep insight of the clock scheduling at the arbitrary phase shifts of clock signals. Moreover, an optimization algorithm is applied to find an optimal phase shift of a clock signal in order to maximize noise suppressions at a specific frequency band. The experimental results on a Xilinx field-programmable gate array Spartan-3 (XC3S400-TQ144) show that the estimated noise reduction rates well-match the measured ones. In these tests, dummy logics are used as noise injectors. This paper also presents a design example with a data encryption standard cryptoprocessor to demonstrate the applicability of our approach. The experiments show that the highest error between the estimated and the measured results is about 2.5 dB. Interestingly, our approach seems to be appropriately used with the designs in wireless communications where designers address to minimize the digital switching noise at the specific frequency bands of interest.

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES

The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naïve implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

FPGA Implementation of a Functional Neuro-Fuzzy Network for Nonlinear System Control

This study used Xilinx Field Programmable Gate Arrays (FPGAs) to implement a functional neuro-fuzzy network (FNFN) for solving nonlinear control problems. A functional link neural network (FLNN) was used as the consequent part of the proposed FNFN model. This study adopted the linear independent functions and the orthogonal polynomials in a functional expansion of the FLNN. Thus, the design of the FNFN model could improve the control accuracy. The learning algorithm of the FNFN model was divided into structure learning and parameter learning. The entropy measurement was adopted in the structure learning to determine the generated new fuzzy rule, whereas the gradient descent method in the parameter learning was used to adjust the parameters of the membership functions and the weights of the FLNN. In order to obtain high speed operation and real-time application, a very high speed integrated circuit hardware description language (VHDL) was used to design the FNFN controller and was implemented on FPGA. Finally, the experimental results demonstrated that the proposed hardware implementation of the FNFN model confirmed the viability in the temperature control of a water bath and the backing control of a car.

Thermal maps based HT detection using spatial projection transformation

Hardware Trojan (HT) is increasingly becoming a serious problem in the information security field. Compared to other countermeasures, thermal maps based detection can mitigate process variation (PV) and have a higher accuracy. However, HT cannot be differentiated from the others directly from the original thermal maps. Therefore, in this study, the authors first propose a general HT detection framework based on difference temperature matrix, and introduce the PV mitigation mechanism. Then, they demonstrate how principal component analysis can implement spatial projection transformation and expose HT signal. Finally, they introduce their experimental setup and design, and then validate their countermeasure with Xilinx field programmable gate arrays which are configured with the pure AES circuit and the infected AES circuits. The power proportions (PPs) of HTs in the different infected AES circuits are various. The experimental results indicate that their proposed countermeasure can clearly detect HT with 0.14% small PP.

Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging

The Gabor filter (GF) has been proved to show good spatial frequency and position selectivity, which makes it a very suitable solution for visual search, object recognition, and, in general, multimedia processing applications. GFs prove useful also in the processing of medical imaging to improve part of the several filtering operations for their enhancement, denoising, and mitigation of artifact issues. However, the good performances of GFs are compensated by a hardware complexity that traduces in a large amount of mapped physical resources. This paper presents three different designs of a GF, showing different tradeoffs between accuracy, area, power, and timing. From the comparative study, it is possible to highlight the strength points of each one and choose the best design. The designs have been targeted to a Xilinx field-programmable gate array (FPGA) platform and synthesized to 90-nm CMOS standard cells. FPGA implementations achieve a maximum operating frequency among the different designs of 179 MHz, while 350 MHz is obtained from CMOS synthesis. Therefore, 86 and 168 full-HD ( $1920 \times 1080$ ) f/s could be processed, with FPGA and std_cell implementations, respectively. In order to meet space constraints, several considerations are proposed to achieve an optimization in terms of power consumption, while still ensuring real-time performances.

High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA

In this paper, a novel high speed and efficient area optimal Ate pairing processor implementation over Barreto-Naehrig (BN) and Barreto-Lynn-Scott (BLS12) curves on field-programmable gate array (FPGA) is proposed. The optimal Ate pairing proposed design, based on two steps: Miller loop and final exponentiation, is specifically optimized for FPGA platforms. The Miller Loop and Final Exponentiation algorithms are optimized and modified for careful scheduling to avoid data dependency and to decrease the number of loops and number of temporary variables required for final exponentiation. Furthermore, suitable multiplier combining Toom-Cook and Karatsuba algorithms is proposed to execute the arithmetical computations needed in pairing architecture processor over Fp.Therefore, an enhancement in terms of pairing computation speed-up and memory resources capacity management is achieved. In this paper, we select the new pairing parameters, especially that has to be used to ensure the 128-bit security level [1]. The proposed optimal Ate pairing architecture at 128 bits security level has been implemented on Xilinx FPGA Virtex6. Our processor implemented over BN curves achieves the highest reported speed together with the best reported area-time performance on Virtex6 (0.35 ms at 225 Mhz). Finally, for BN-446 and BN-638, the pairing proposed processor performances are estimated.