Xilinx Field Programmable Gate Array Research Articles

Rapid Prototyping and Hardware-In-the-Loop Verification of Enhanced Sliding Mode Control of an Asynchronous Machine Using a Xilinx System Generator and an FPGA-Zynq Board

This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA’s parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.

Design and implementation of hardware-software architecture based on hashes for SPHINCS+

Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for proposals to standardize algorithms for post-quantum cryptography (PQC), which is considered difficult to solve for both classical and quantum computers. Among the proposed technologies, the most popular choices are lattice-based (shortest vector problem) and hash-based approaches. Other important categories are public key cryptography (PKE) and digital signatures. Within the realm of digital signatures lies SPHINCS+. However, there are few implementations of this scheme in hardware architectures. In this article, we present a hardware-software architecture for the SPHINCS+ scheme. We utilized a free RISC-V (Reduced Instruction Set Computer) processor synthesized on a Field Programmable Gate Array (FPGA), primarily integrating two accelerator modules for Keccak-1600 and the Haraka hash function. Additionally, modifications were made to the processor to accommodate the execution of these added modules. Our implementation yielded a 15-fold increase in performance with the SHAKE-256 function and nearly 90-fold improvement when using Haraka, compared to the reference software. Moreover, it is more compact compared to related works. This implementation was realized on a Xilinx FPGA Arty S7: Spartan-7.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

A Crypto Accelerator of Binary Edward Curves for Securing Low-Resource Embedded Devices

This research presents a novel binary Edwards curve (BEC) accelerator designed specifically for resource-constrained embedded systems. The proposed accelerator incorporates the fixed window algorithm, a two-stage pipelined architecture, and the Montgomery radix-4 multiplier. As a result, it achieves remarkable performance improvements in throughput and resource utilization. Experimental results, conducted on various Xilinx Field Programmable Gate Arrays (FPGAs), demonstrate impressive throughput/area ratios observed for GF(2233). The achieved ratios for Virtex-4, Virtex-5, Virtex-6, and Virtex-7 are 12.2, 19.07, 36.01, and 38.39, respectively. Furthermore, the processing time for one-point multiplication on a Virtex-7 platform is 15.87 µs. These findings highlight the effectiveness of the proposed accelerator for improved throughput and optimal resource utilization.

Security Issues of GPUs and FPGAs for AI-powered near & far Edge Services

Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) are widely applied to cloud and embedded applications in which such devices are applied to near and far edge computing operations. This pool of available devices has a wide range of power/size specifications to support servers ranging from big data centres to small cloudlets, or even down to embedded systems and IoT boards. Overall, the most prominent devices and vendors in the market today are the following Xilinx for FPGA-based accelerators, Nvidia and AMD for GPUs, Intel for FPGA- /GPU-based accelerators. Decreasing the latency and increasing the throughput of Artificial Intelligence Functions (AIF), either for network automation or user applications, requires some sort of parallelization inside such purpose-built hardware acceleration. The AI@EDGE project is developing a Connect-Compute Platform (CCP) in which hardware accelerators (1 Nvidia GPU Tesla V100 (near edge device) and 1 Jetson AGX and 1 Jetson Nano (far edge devices), as well as 2 Xilinx FPGAs Alveo U280+U200 (near edge devices) and 1 Versal VCK190 and 2 Zynq ZCU104) are placed inside a server node and execute edge computing scenarios involving multiple nodes of diverse compute capabilities each, to test various integration approaches, to study orchestration techniques measure AIF deployment efficiency, all while developing certain FPGA/GPU code to accelerate representative AIFs of AI@EDGE. In this paper we compare the power/size/performance specifications of all accelerators and highlight the security issues associated with the cloud and embedded accelerators. This study presents the security issues announced by the vendors with the results of our tests and proposes tests and security functions (policies and objectives) which will be applied to the CCP to increase the security level of CCP. It also considers security issues related with the hardware set-up (accelerators inside server nodes) from the network point of view.

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA.

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes

Finite field arithmetic operations over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{GF}(2^{m})$</tex-math></inline-formula> are widely used in critical applications, such as cryptography, coding theory, error-correcting codes, and digital signal processing. Finite field inversions are the most time-consuming operations among other widely-used ones and require a large footprint as well as power/energy to be performed. To reduce such complexity, the Itoh–Tsujii algorithm (ITA) has received prominent attention in the literature; however, implementations using ITA are still vulnerable to natural very-large-scale integration defects. To overcome the challenge of detecting naturally-induced faults in such constructions, for the first time, we propose error detection schemes based on Hamming codes for architectures performing finite field inversions using the ITA algorithm over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{GF}(2^{m})$</tex-math></inline-formula> with polynomial basis. Additionally, CRC-oriented error detection schemes for inversions in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\text{GF}(2^{m})$</tex-math></inline-formula> with normal basis are also studied and new approaches to protect them are presented. In this article, general formulations are provided along with different case studies to show the feasibility of our schemes with any finite field size. Moreover, field-programmable gate array (FPGA) implementations are performed on two Xilinx FPGA families, i.e., Kintex UltraScale+ and Xilinx Virtex-7 UltraScale+, to verify that the overheads added by the error detection architectures to provide reliability are suitable for deeply-constrained embedded systems.

Quantization-Aware NN Layers with High-throughput FPGA Implementation for Edge AI

Over the past few years, several applications have been extensively exploiting the advantages of deep learning, in particular when using convolutional neural networks (CNNs). The intrinsic flexibility of such models makes them widely adopted in a variety of practical applications, from medical to industrial. In this latter scenario, however, using consumer Personal Computer (PC) hardware is not always suitable for the potential harsh conditions of the working environment and the strict timing that industrial applications typically have. Therefore, the design of custom FPGA (Field Programmable Gate Array) solutions for network inference is gaining massive attention from researchers and companies as well. In this paper, we propose a family of network architectures composed of three kinds of custom layers working with integer arithmetic with a customizable precision (down to just two bits). Such layers are designed to be effectively trained on classical GPUs (Graphics Processing Units) and then synthesized to FPGA hardware for real-time inference. The idea is to provide a trainable quantization layer, called Requantizer, acting both as a non-linear activation for neurons and a value rescaler to match the desired bit precision. This way, the training is not only quantization-aware, but also capable of estimating the optimal scaling coefficients to accommodate both the non-linear nature of the activations and the constraints imposed by the limited precision. In the experimental section, we test the performance of this kind of model while working both on classical PC hardware and a case-study implementation of a signal peak detection device running on a real FPGA. We employ TensorFlow Lite for training and comparison, and use Xilinx FPGAs and Vivado for synthesis and implementation. The results show an accuracy of the quantized networks close to the floating point version, without the need for representative data for calibration as in other approaches, and performance that is better than dedicated peak detection algorithms. The FPGA implementation is able to run in real time at a rate of four gigapixels per second with moderate hardware resources, while achieving a sustained efficiency of 0.5 TOPS/W (tera operations per second per watt), in line with custom integrated hardware accelerators.

An efficient FPGA‐based implementation of UWB radar system for through‐wall imaging

SummaryThe work presented in this paper aims to develop a low‐cost ultra‐wideband (UWB) radar system that has the capability to image through the wall of a human target. The proposed radar system relies heavily on a field‐programmable gate array (FPGA) platform. The Xilinx FPGA Kintex‐7 (KC705) board is employed to integrate the main functionalities of the radar system, such as the generation and acquisition of a UWB signal. The generated signal is a monocycle signal, which has an ultra‐wide bandwidth. Due to the UWB nature of this signal, the radar system achieves better penetration ability, as well as high imaging resolution. However, the major challenge of a UWB radar system lies in the stage of digitization, as it requires a high sampling rate analog‐to‐digital converter (ADC). In fact, such a chip is very expensive. Hence, to reach a high sampling resolution using a low‐cost and low‐speed ADC, an efficient sampling strategy is implemented. In contrast to other UWB sampling methods, which require a hardware delay line chip, the new sampling scheme depends only on the FPGA firmware to realize a combination of real‐time and equivalent‐time sampling, which provides better jitter performance. Finally, to demonstrate the imaging capability, experimental tests are conducted in an indoor environment while human targets are located in different places. The measurement results revealed that the proposed radar system has the ability to provide 2D images that accurately determine the location of the target.

ИССЛЕДОВАНИЕ ПАРАМЕТРОВ ФИЗИЧЕСКИ НЕКЛОНИРУЕМОЙ ФУНКЦИИ ТИПА АРБИТР ПРИ РЕАЛИЗАЦИИ НА ПЛИС

The influence of various circuitry solutions of a physically unclonable function (PUF) of the arbiter type and the location of their logical blocks on the parameters of the PUF are investigated. The increasing proliferation and use of Internet of Things (IoT) technologies and, accordingly, devices connected to cellular and Internet networks, an urgent problem is to ensure the security and confidentiality of data access. It should be noted that IoT devices are demanding on a number of parameters, such as power consumption, integrated circuit geometric dimensions, and the requirement to protect against cyberattacks. As a simple, cost-effective and universal solution, hardware methods of physical cryptography proved to be the most preferred. Physically unclonable functions can be implemented in various devices by designing their circuits based on field-programmable gate arrays (FPGA). The Xilinx FPGA of the Zynq-7000 family has been used for this study. This approach gives greater flexibility in terms of the architecture used and allows the system to be more precisely adapted to any need. EBAZ4205 and AntMiner_v1.0 FPGA debug boards based on the XC7Z010CLG400-1 platform with two built-in ARM Cortex-A9 processor cores have been used as monitoring and measuring equipment. The method of physical cryptography of devices is considered. Several configuration bitstreams of PUF the arbiter-type firmware with different arrangement of functional blocks on a chip have been developed and implemented. All configurations have been tested, and the results were shown to change depending on the PUF location on the chip. An important task while implementing the PUF of the arbiter type on any hardware platform is to equalize the lengths of the signal propagation lines. This can be achieved both by adding additional delay blocks on the line, and by increasing the length of the routed signal line. In this study the best results were obtained with manual routing and a "vertical" arrangement of the logical blocks of the circuit.

FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

This paper presents a discrete-time synergetic controller (DTSC) enhanced with ant colony optimization (ACO) technique for a shunt active power filter (SAPF). The developed controller is designed under MATLAB/Simulink environment; then, field-programmable gate array (FPGA) in the loop (FIL) technique is used to implement the DTSC model. The proposed DTSC parameters are optimally tuned according to ACO methodology. The DTSC-ACO should enhance power quality and eliminate grid current harmonics using an indirect current-controlled three-phase SAPF. Note that, the designed FPGA controller integrates the items needed to drive the SAPF. This digital implementation satisfies the hardware and recommended performance. In fact, it reduces significant resources and execution time. The experimental validation is carried out on Virtex-6 ML605 FPGA Xilinx Evaluation Kit using VIVADO processing. A total harmonic distortion (THD = 2.72%) is obtained for the grid current. Thus, the results obtained confirm proper operation of the developed approach. In addition, the proposed DTSC shows good dynamic performance during load step change and output voltage variation.

Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.

FPGA-based 4 × 29.4912 Gbit/s PS-PAM4 signal transmission with a low-complexity probabilistic shaping scheme.

In this experiment, we demonstrate a real-time intensity modulation and direct detection (IM/DD) system based on a field programmable gate array (FPGA). For high-speed parallel signal processing, we propose and implement the simplified parallel-constant modulus algorithm (CMA) and decision-directed least mean square (DDLMS) equalizers with low complexity and low latency. Moreover, the bit-class probabilistic shaping (PS) scheme is adopted with very few hardware resources. The digital signal processing (DSP) steps are implemented in the XCVU9P-FLGB2104-2-I Xilinx FPGA with a clock frequency of 230.4 MHz. Based on the experimental results, 4 × 29.4912 Gbit/s PS-pulse amplitude modulation (PAM4) signals can be successfully transmitted over 25 km of standard single-mode fiber (SSMF) while satisfying the hard-decision forward error correction (HD-FEC) threshold at 3.8 × 10-3. Compared with the uniformly distributed PAM4 signal, the low-complexity PS scheme can improve the receiver sensitivity by more than 1 dB.

FPGA-based implementation of deep neural network using stochastic computing

A serious challenge in artificial real-time applications is the hardware implementation of deep neural networks (DNN). Among various methods, stochastic computing (SC)-based implementations received tremendous attention due to the low hardware overhead. However, the slow convergence rate is a major problem in SC-based neural networks’ implementation, and millions of clock cycles are required to generate a relatively accurate output. The reconfigurability and parallel nature of field programmable gate array (FPGA) chips make them a preferable platform for SC-based DNN implementation. A fully or semi-parallel implementation of DNNs requires extensive hardware resources. In this paper, an efficient method for DNN implementation on an FPGA chip is presented to address these problems. The FPGA chip reconfiguration feature allows a DNN with several different neurons and topologies to be implemented on a single chip. Convergence time is significantly reduced by limiting the length of the stochastic bitstreams and establishing synchronization between the processing units based on precise timing. Furthermore, due to the limited number of input–output pins in the FPGA chip, a sequential architecture is proposed wherein the DNN inputs enter through only three 8-bit ports. This makes it possible to implement DNNs for image-processing applications. The proposed method is implemented using the Verilog hardware description language on the Xilinx FPGA Virtex-7 xc7v2000t chip. The results show a more than 82% reduction in hardware resources and the minimum rate of power consumption compared to state-of-the-art methods. In addition, the average error rate of the implemented DNN is reduced by 2%.

Learning Malicious Circuits in FPGA Bitstreams

Computing platforms are integrating field-programmable gate arrays (FPGAs) to support domain-specific customization. Multiple tenants can share these FPGAs by configuring them at runtime. However, attackers can abuse this capability by programming the FPGAs with malicious functions. A malicious configuration bitstream can launch denial of service, overheat the FPGA, leak sensitive information via side channels, enable remote monitoring, and launch voltage and timing attacks. We consider time-based multitenancy, where multiple tenants use the FPGA at different time intervals and not at the same time. We propose a defense based on machine learning (ML) algorithms to detect bitstreams of malicious circuits and malicious circuits mixed with legitimate circuits by analyzing the static features extracted from FPGA bitstreams. The proposed approach can help detect malicious bitstreams without the need for reverse engineering of the bitstream or having access to the design netlist. Our results on Xilinx FPGAs indicate that supervised classifiers may identify malicious bitstreams representing ring-oscillator circuits with a true-positive rate (TPR) of 100% and a false-positive rate (FPR) of only 4%. In addition, for the extremely difficult problem of detecting malicious bitstreams embedded in legitimate bitstreams, a pipeline of a random forest and a support vector machine classifiers trained on subarrays of bitstreams can help detect bitstreams of malicious circuits embedded in legitimate designs with TPR of 95.5% and FPR of 30.4%.

RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability

Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-Programmable Gate Array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the benchmark design (libSGM) working on the Tegra X2 GPU, RT-libSGM runs more than 2× faster at a much lower energy cost.

Precision Hall Effect magnetometer.

The article presents a Hall effect magnetometer for use in a desktop Electron Paramagnetic Resonance spectrometer with a permanent magnet system and scanning coils. High accuracy and long-term stability at a small size and low cost are achieved through the use of digital signal processing, sequential data filtering in the time and frequency domains, as well as digital correction of raw data based on calibration information. The exciting current of the Hall sensor has the form of an alternating-signsquare wave formed by a high-speed H-bridge powered by a stable direct current. Generation of control signals, time selection of data, and their accumulation are performed using Xilinx Field-Programmable Gate Array Artix-7. MicroBlaze embedded 32-bit processor is used to control the magnetometer and interface with adjacent levels of the control system. Taking into account the individual characteristics of the sensor, including the offset voltage, the nonlinearity of the magnetic sensitivity, and their temperature dependences, is carried out by correcting the data obtained by calculating a polynomial depending on the raw magnitude of the field induction and the temperature of the sensor. The polynomial coefficients are individual for each sensor, are determined once during the calibration process, and are stored in the dedicated Electrically Erasable Programmable Read-Only Memory. The magnetometer has a high resolution of 0.1 µT and an absolute measurement error of not exceeding 6 µT.