ИССЛЕДОВАНИЕ ПАРАМЕТРОВ ФИЗИЧЕСКИ НЕКЛОНИРУЕМОЙ ФУНКЦИИ ТИПА АРБИТР ПРИ РЕАЛИЗАЦИИ НА ПЛИС

Abstract

The influence of various circuitry solutions of a physically unclonable function (PUF) of the arbiter type and the location of their logical blocks on the parameters of the PUF are investigated. The increasing proliferation and use of Internet of Things (IoT) technologies and, accordingly, devices connected to cellular and Internet networks, an urgent problem is to ensure the security and confidentiality of data access. It should be noted that IoT devices are demanding on a number of parameters, such as power consumption, integrated circuit geometric dimensions, and the requirement to protect against cyberattacks. As a simple, cost-effective and universal solution, hardware methods of physical cryptography proved to be the most preferred. Physically unclonable functions can be implemented in various devices by designing their circuits based on field-programmable gate arrays (FPGA). The Xilinx FPGA of the Zynq-7000 family has been used for this study. This approach gives greater flexibility in terms of the architecture used and allows the system to be more precisely adapted to any need. EBAZ4205 and AntMiner_v1.0 FPGA debug boards based on the XC7Z010CLG400-1 platform with two built-in ARM Cortex-A9 processor cores have been used as monitoring and measuring equipment. The method of physical cryptography of devices is considered. Several configuration bitstreams of PUF the arbiter-type firmware with different arrangement of functional blocks on a chip have been developed and implemented. All configurations have been tested, and the results were shown to change depending on the PUF location on the chip. An important task while implementing the PUF of the arbiter type on any hardware platform is to equalize the lengths of the signal propagation lines. This can be achieved both by adding additional delay blocks on the line, and by increasing the length of the routed signal line. In this study the best results were obtained with manual routing and a "vertical" arrangement of the logical blocks of the circuit.