FPGA-Based Hardware in the Loop of Optimized Synergetic Controller for Active Power Filter

Abstract

This paper presents a discrete-time synergetic controller (DTSC) enhanced with ant colony optimization (ACO) technique for a shunt active power filter (SAPF). The developed controller is designed under MATLAB/Simulink environment; then, field-programmable gate array (FPGA) in the loop (FIL) technique is used to implement the DTSC model. The proposed DTSC parameters are optimally tuned according to ACO methodology. The DTSC-ACO should enhance power quality and eliminate grid current harmonics using an indirect current-controlled three-phase SAPF. Note that, the designed FPGA controller integrates the items needed to drive the SAPF. This digital implementation satisfies the hardware and recommended performance. In fact, it reduces significant resources and execution time. The experimental validation is carried out on Virtex-6 ML605 FPGA Xilinx Evaluation Kit using VIVADO processing. A total harmonic distortion (THD = 2.72%) is obtained for the grid current. Thus, the results obtained confirm proper operation of the developed approach. In addition, the proposed DTSC shows good dynamic performance during load step change and output voltage variation.