Worst-case Execution Time Estimates Research Articles

Static probabilistic worst case execution time estimation for architectures with faulty instruction caches

Semiconductor technology evolution suggests that permanent failure rates will increase dramatically with scaling, in particular for SRAM cells. While well known approaches such as error correcting codes exist to recover from failures and provide fault-free chips, they will not be affordable anymore in the future due to their growing cost. Consequently, other approaches like fine-grained disabling and reconfiguration of hardware elements (e.g. individual functional units or cache blocks) will become economically necessary. This fine-grained disabling will degrade performance compared to a fault-free execution. To the best of our knowledge, all static worst-case execution time (WCET) estimation methods assume fault-free processors. Their result is not safe anymore when fine-grained disabling of hardware components is used. In this paper we provide the first method that statically calculates a probabilistic WCET bound in the presence of permanent faults in instruction caches. The proposed method derives a probabilistic WCET bound for a program, cache configuration, and probability of cell failure. As our method relies on static analysis to bound the longest path, its probabilistic nature only stems from the probability that faults actually occur. Our method is computationally tractable because it does not require an exhaustive enumeration of all the possible combinations of faulty cache blocks. Experimental results show that it provides WCET estimates very close to, but never below, the method that derives probabilistic WCETs by enumerating all possible locations of faulty cache blocks. The proposed method not only allows to quantify the impact of permanent faults on WCET estimates, but, most importantly, can be used in architectural exploration frameworks to select the most appropriate fault management mechanisms and design parameters for current and future chip designs.

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments

Critical real-time embedded systems (CRTES), which are deployed in cars, planes, and satellites, among other domains, feature increasingly complex safety-related, performance-demanding functionality. Realistically, such functionality can be provided by means of advanced (high-performance) hardware and software. This will inevitably shift CRTES from using simple control software running on in-order, single-core processors with no caches to complex multisensor and multiactuator software running on aggressive processors implemented in nanoscale technology deploying several computing cores and a cache hierarchy. However, the use of aggressive technologies and architectures challenges time predictability and reliability, which are mandatory features in CRTES. The authors present a processor design that reconciles all three goals--namely, predictability, reliability, and high performance. Their design obtains trustworthy and tight worst-case execution time (WCET) estimates for safety-critical applications running on high-performance hardware facing hard and soft errors by means of a smart use of timing-analysis techniques in combination with minor hardware modifications.

An Overview of Worst-Case Execution Time Estimation for Embedded Programs

Most embedded systems are real-time systems, so real-time is an important performance metric for embedded systems. The worst-case execution time (WCET) estimation for embedded programs could satisfy the requirement of hard real-time evaluation, so it is widely used in embedded systems evaluation. Based on sufficient survey on the progress of WCET estimation around the world, it proposes a new classification of WCET estimation. After introducing the principle of WCET estimation, it mainly demonstrates various types of technologies to estimate WCET and classifies them into two main streams, namely, static and dynamic WCET estimations. Finally, it shows the development of WCET analysis tools.

A Unified WCET analysis framework for multicore platforms

With the advent of multicore architectures, worst-case execution time (WCET) analysis has become an increasingly difficult problem. In this article, we propose a unified WCET analysis framework for multicore processors featuring both shared cache and shared bus. Compared to other previous works, our work differs by modeling the interaction of shared cache and shared bus with other basic microarchitectural components (e.g., pipeline and branch predictor). In addition, our framework does not assume a timing anomaly free multicore architecture for computing the WCET. A detailed experiment methodology suggests that we can obtain reasonably tight WCET estimates in a wide range of benchmark programs.

Safety-critical medical device development using the UPP2SF model translation tool

Software-based control of life-critical embedded systems has become increasingly complex, and to a large extent has come to determine the safety of the human being. For example, implantable cardiac pacemakers have over 80,000 lines of code which are responsible for maintaining the heart within safe operating limits. As firmware-related recalls accounted for over 41% of the 600,000 devices recalled in the last decade, there is a need for rigorous model-driven design tools to generate verified code from verified software models. To this effect, we have developed the UPP2SF model-translation tool, which facilitates automatic conversion of verified models (in UPPAAL) to models that may be simulated and tested (in Simulink/Stateflow). We describe the translation rules that ensure correct model conversion, applicable to a large class of models. We demonstrate how UPP2SF is used in the model-driven design of a pacemaker whose model is (a) designed and verified in UPPAAL (using timed automata), (b) automatically translated to Stateflow for simulation-based testing, and then (c) automatically generated into modular code for hardware-level integration testing of timing-related errors. In addition, we show how UPP2SF may be used for worst-case execution time estimation early in the design stage. Using UPP2SF, we demonstrate the value of integrated end-to-end modeling, verification, code-generation and testing process for complex software-controlled embedded systems.

Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems

Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.

Petri Net-Based FTL Architecture for Parametric WCET Estimation via FTL Operation Sequence Derivation

A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones.

A comparison of instruction memories from the WCET perspective

Abstract Hard real-time systems demand high performance in combination with a timing predictable program execution. The performance of a system in the worst-case, represented by its worst case execution time (WCET), highly depends on the design of the memory subsystem. In this paper we focus on the instruction memory hierarchy and quantify the impact of different on-chip instruction memories on the worst-case timing of the system. A function-based dynamic instruction scratchpad (D-ISP), an instruction cache, and static instruction scratchpads using basic-block-based and function-based assignment algorithms are compared. Therefore, we provide WCET bounds for systems with different on-chip instruction memories and different off-chip memory timings. We show that for small memory sizes a static instruction scratchpad usually outperforms the other memories in terms of the WCET estimate. However, with increasing memory sizes the D-ISP is able to reach lower WCET bounds. An instruction cache can only provide lower WCET bounds than the other memories, if no suitable assignment for the static instruction scratchpads is found or if the D-ISP suffers from thrashing or frequently loads unused code.

A Worst-Case Execution Time Analysis Approach Based on AOE Networks

To overcome disadvantages of traditional worst-case execution time (WCET) analysis approaches, this paper proposes a new WCET analysis approach based on AOE networks for ARM programs. By assigning the execution times of program segments to weights of directed edges, we reformulated the analysis of the WCET of the program as finding the longest path in a weighted directed graph. An algorithm implemented in this paper is used to search the longest path in the weighted directed graph and gives the WCET estimate finally. Experimental results have shown the analysis approach proposed in this paper is an effective way to obtain the safe and tight WCET estimate for ARM programs.

Guest Editorial: From Uniprocessors to Multiprocessors: Advances in Real-Time Systems

Real-time multiprocessor computing has been an active area of research for many years. For example, several real-time multiprocessor scheduling results are known for more than three decades. However, while the field of real-time uniprocessor computing evolved steadily to a mature area, the multiprocessor counterpart lagged behind, plagued by higher intrinsic complexity, costly platforms, low efficiency and few applications. This situation changed radically in the last decade with the massification of multi-core processors that made parallel computing platforms available in practically all general purpose computers as well as many industrial and embedded systems. This revolution forced adaptations in many existing software commodities to take advantage of the available parallel computing hardware and motivated a strong research effort in tackling the idiosyncrasies of these systems. The real-time systems community in particular has been dedicating substantial attention to issues such as the definition of analysable task models that better adapt to parallel platforms, the scheduling of the tasks on the set of processors, the tasks synchronization across processors and the access to global resources including caches, to name just a few. This special issue includes four recent works that are representative of the state of the art in real-time multiprocessor computing. These are follow-ups of the four papers that were nominated for the Best and Student Best Paper Awards at RTSS 2011, the 32nd IEEE Real-Time Systems Symposium. Three of them address task scheduling issues while the fourth addresses worst-case execution time estimation. Moreover,

Cache persistence analysis

To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis [Ferdinand 1997] are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses. There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this article, we present a correctness issue with this analysis. To fix this issue, we propose two new abstract interpretation based persistence analyses and show their safety. One is based on the known may analysis and a second one on the concept of conflict counting. For fully timing compositional architectures [Wilhelm et al. 2009] the persistence information is straightforward to use. We will apply the concepts of persistence analysis for the first time to state-of-the-art architectures that exhibit both timing anomalies and domino effects. Such architectures do not allow the analyzer to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the presented novel persistence analyses together with a novel path analysis approach into the industrially used WCET analyzer aiT.

A Worst-case execution time analysis approach based on independent paths for ARM programs

To overcome disadvantages of traditional worst-case execution time (WCET) analysis approaches, we propose a new WCET analysis approach based on independent paths for ARM programs. Based on the results of program flow analysis, it reduces and partitions the control flow graph of the program and obtains a directed graph. Using linear combinations of independent paths of the directed graph, a set of feasible paths can be generated that gives complete coverage in terms of the program paths considered. Their timing measurements and execution counts of program segments are derived from a limited number of measurements of an instrumented version of the program. After the timing measurement of the feasible paths are linearly expressed by the execution times of program segments, a system of equations is derived as a constraint problem, from which we can obtain the execution times of program segments. By assigning the execution times of program segments to weights of edges in the directed graph, the WCET estimate can be calculated on the basis of graph-theoretical techniques. Comparing our WCET estimate with the WCET measurement obtained by the exhaustive measurement, the maximum error ratio is only 8.259 3 %. It is shown that the proposed approach is an effective way to obtain the safe and tight WCET estimate for ARM programs.

Static Analysis of Run-Time Inter-Core Interferences for Concurrent Programs in Shared Cache Multicore Architectures

Worst-Case Execution Time (WCET) is crucial in real-time systems and is very challenging in multicore processors due to the possible runtime inter-thread interferences caused by shared resources. This paper proposes a novel approach to analyze runtime inter-core interferences for consecutive or inconsecutive concurrent programs. Our approach can reasonably estimate runtime inter-core interferences in shared cache by introducing lifetime and instruction fetching timing relations analysis into address mapping method. Compared with the method based on lifetime alone, our proposed approach efficiently improves the tightness of WCET estimation.

A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors

As multicore processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multicore chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multicores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimated statically. This article proposes an approach to analyzing WCET for multicore processors with shared L2 instruction caches by using a model checking based method. We model each concurrent real-time thread, including the inter-thread cache interferences with a PROMELA process, and derive the WCET by using a binary search algorithm. To reduce the state explosion problem, we propose several techniques for reducing the memory consumption by exploiting domain-specific information. Our experiments indicate that compared to the static analysis technique based on extended ILP (integer linear programming), our approach improves the tightness of WCET estimation by more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multicore timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors.

Worst Case Execution Time Analysis of Automotive Software

Knowing the program timing characteristics is fundamental to the successful design and execution of real-time systems. The Worst-Case Execution Time (WCET) of a program is the longest execution time that will ever be observed when the program is run on its target hardware. The WCET is needed for many different types of system analysis for real-time systems. Timing becomes the most important factor while considering the distributed automotive embedded real-time systems. Handling real-time constraints to add more functionality to a vehicle is required while modelling these systems. In this present study the WCET estimate is obtained by measurement-based method using in-circuit emulator for a given set of input data. Many existing methods of WCET analysis require the availability of the source code of the program in order to estimate WCET. Here, the measurement-based analysis is performed which is solely based on execution traces of the program and is independent of the program semantics.

Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems

Power demand grows much faster than battery capacity in embedded systems. Dynamic voltage and frequency scaling (DVFS) has been shown to be extremely efficient to save energy due to the exponential dependence of power on voltage. However, voltage/frequency cannot be blindly scaled in hard real-time systems because DVFS techniques impact on the execution time, and so potentially on the worst-case execution time (WCET) of tasks. This paper presents a new DVFS technique for hard real-time systems that measures dynamically the intra-task slack existing between the actual execution time of a task and its WCET estimation, and exploits it to perform DVFS guaranteeing that the WCET is not affected. Concretely, our approach exploits the slack available due to contention in the use of shared resources in a multi-core system.

A new way about using statistical analysis of worst-case execution times

In this paper, we revisit the problem of using Extreme Value Theory (EVT) in the Worst-Case Execution Time (WCET) analysis of the programs running on a single processor. Our proposed statistical WCET analysis method consists of a novel sampling mechanism tackling with some problems that hindered the application of using EVT in the context, and a statistical inference about computation of a WCET estimate of the target program. To be specific, the presented sampling mechanism takes analysis samples from the target program based around end-to-end measurements. Next, the statistical inference using EVT together with other statistical techniques, analyzes such timing traces which contain the execution time data of the program, to compute a WCET estimate with a certain predictable probability of being exceeded.

Worst‐case execution time analysis‐driven object cache design

SUMMARYHard real‐time systems need a time‐predictable computing platform to enable static worst‐case execution time (WCET) analysis. All performance‐enhancing features need to be WCET analyzable. However, standard data caches containing heap‐allocated data are very hard to analyze statically. In this paper we explore a new object cache design, which is driven by the capabilities of static WCET analysis. Simulations of standard benchmarks estimating the expected average case performance usually drive computer architecture design. The design decisions derived from this methodology do not necessarily result in a WCET analysis‐friendly design. Aiming for a time‐predictable design, we therefore propose to employ WCET analysis techniques for the design space exploration of processor architectures. We evaluated different object cache configurations using static analysis techniques. The number of field accesses that can be statically classified as hits is considerable. The analyzed number of cache miss cycles is 3–46% of the access cycles needed without a cache, which agrees with trends obtained using simulations. Standard data caches perform comparably well in the average case, but accesses to heap data result in overly pessimistic WCET estimations. We therefore believe that an early architecture exploration by means of static timing analysis techniques helps to identify configurations suitable for hard real‐time systems. Copyright © 2011 John Wiley & Sons, Ltd.

Identifying irreducible loops in the Instrumentation Point Graph

The Instrumentation Point Graph (IPG) is a program model whose primary usage is within hybrid measurement-based frameworks that compute Worst-Case Execution Time (WCET) estimates. The IPG represents the transitions between instrumentation points (Ipoints) that are inserted into the program to collect measurements at run time. However, uncontrolled Ipoint placement often causes the resultant IPG to contain unstructured (i.e. irreducible) loops, potentially compromising the safety of WCET estimates unless the hierarchical containment among IPG loops can be correctly identified. The contributions of this paper are fourfold: (1) we show that the IPG is more susceptible to irreducibility even when the program itself is well structured; (2) we demonstrate that state-of-the-art loop detection algorithms, designed specifically to handle irreducible loops, generally fail to construct the correct hierarchical relationship between IPG loops; (3) we present an algorithm that identifies arbitrary irreducible loops in the IPG during its construction from another graph-based model, an extended type of Control Flow Graph (CFG) called the CFG^*; (4) we show how the structural relation between the IPG and the CFG^* allows loop bounds obtained through static analysis to be transferred onto the IPG.

Cache persistence analysis

To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses. There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this paper, we present a correctness issue with this analysis and a novel analysis that fixes it. For fully timing compositional architectures the persistence information is straightforward to use. We will focus on the application of the persistence analysis for state-of-the-art architectures that show timing anomalies. Such architectures do not allow to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the novel persistence analysis together with a novel path analysis approach into the industrially used WCET analyzer aiT.