Worst Case Bias Conditions Research Articles

Impact of Varied Buffer Layer Designs on Single-Event Response of 1.2-kV SiC Power MOSFETs

In this article, the single-event response of the 1.2-kV silicon-carbide (SiC) power MOSFETs with varied buffer layer designs is investigated by the 2-D numerical simulations. The structural parameters of the buffer layers are compared and analyzed to understand the transient response after the heavy ion strike and the related physical mechanisms comprehensively. Simulation results reveal that an optimized single buffer structure can be acquired by using a relatively thicker buffer layer (T $\mu \text{m}$ ) and a moderate doping concentration (D cm−3). It demonstrates that the single-event-burnout (SEB) performance can be improved significantly under the worst case bias conditions [a drain bias voltage of 1.2 kV and a linear energy transfer (LET) of 1 pC/ $\mu \text{m}$ ]. In addition, the optimized structural combinations adopted in the dual or triple buffer layers can strengthen the SEB performance further. The simulation results show that a step electric field distribution is established inside the optimized dual or triple buffers, where the electric field peak is mitigated from 3 to 2.2 MV/cm. Moreover, the excess carrier generation is suppressed and the local temperature rise is weakened during the transient electrothermal process. Consequently, the structure with the optimal buffer layer designs can enlarge the SEB safe operating area (SOA) from 30%–50% to 100% rated breakdown voltage at high LET bias, which makes the SiC power MOSFETs used in aerospace and aviation power electronic systems become possible.

Accelerated Tests on Si and SiC Power Transistors with Thermal, Fastand Ultra-Fast Neutrons.

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed.

Comparison of the Total Dose Responses of Fully Depleted SOI nMOSFETs With Different Geometries for the Worst Case Bias Conditions

Fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs fabricated using 0.2- $\mu \text{m}$ SOI technology with external body contact (EBC) and floating body (FB) structures are irradiated up to 500 krad(Si) using 60Co gamma rays under the transmission gate (TG) and OFF bias conditions, respectively. The threshold voltage shift of the back transistors due to radiation-induced charge trapping in the buried oxide (BOX) is used to characterize the total dose response of irradiated back transistors. The results indicate that, overall, the TG biased EBC transistors with various gate lengths are more sensitive to the total dose radiation than the OFF biased FB counterparts at low dose levels. Furthermore, for the shorter gate transistors with a supply voltage of 1.8 V, a relatively complex correlation exists between the total dose response and the gate length. In particular, the back transistor of the TG biased 0.20- $\mu \text{m}$ 1.8-V EBC transistor reveals smaller threshold voltage shifts than the OFF biased counterpart at approximately 500 krad(Si) because of the saturation of its threshold shift with increased doses, and a similar radiation response is observed for the TG biased 0.35- $\mu \text{m}$ EBC transistor with a supply voltage of 2.5 V. We found that the 2.5-V back transistors exhibited greater radiation hardness than the 1.8-V counterparts with the same bias configuration in most cases.

Charge Buildup and Spatial Distribution of Interface Traps in 65-nm pMOSFETs Irradiated to Ultrahigh Doses

In this paper, a commercial 65-nm CMOS technology is irradiated at ultrahigh ionizing doses and then annealed at high temperature under different bias conditions. The experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. We find that the charge buildup in the spacers is insensitive to the applied source-to-drain electric field, but the generation and/or annealing of interface traps strongly depends on applied drain bias and channel length. The static dc and charge-pumping measurements indicate a high density of interface traps in the lateral source/drain extension regions. The worst case bias condition corresponds to the application of a large drain–source voltage, due to the lateral electric field driving hydrogen from the spacers toward the source extension and the channel. The consequent differences in growth and annealing rates of interface traps lead to a large asymmetric degradation of the short-channel transistors. The technology computer-aided design simulations are used to qualitatively confirm the proposed degradation model.

Worst-Case Bias for Proton and 10-keV X-Ray Irradiation of AlGaN/GaN HEMTs

Responses to 1.8 MeV proton irradiation and 10-keV X-ray irradiation under typical bias conditions are investigated for AlGaN/GaN HEMTs fabricated with different types of process technologies. We find that, in contrast to previous generations of process technologies, total ionizing dose effects can be significant in these devices. For proton irradiation, worst-case bias for transconductance degradation for GaN-on-SiC substrate devices is ON bias, and for devices built on free-standing GaN substrates, the worst-case bias condition is semi-ON bias. Low-frequency noise measurements demonstrate that these differences result from differences in defect types and energy distributions for the different types of devices, both before and after irradiation. These results emphasize the need to test devices under a wide range of conditions during characterization and qualification testing.

Impact of bias conditions on electrical stress and ionizing radiation effects in Si-based TFETs

The interplay between electrical stress and ionizing radiation effects is experimentally investigated in Si-based Tunnel Field Effect Transistors (TFETs). In particular, the impact of bias conditions on the performance degradation is discussed. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, the worst-case bias condition for studying radiation effects is not straightforward to be determined when there is an interplay between electrical stress and ionizing radiation effects.

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

A silicon-on-insulator (SoI)-like bulk silicon (SLBS) MOSFET structure is studied and compared against a fully depleted (FD) SoI MOSFET using 2-D numerical simulations. A p/n - /p + structure was contained in SLBS device, in which n - is made of 4H-SiC. This n - layer is FD. Hot carrier (HC) effects (HCEs) in proposed SLBS nMOSFET were simulated and compared with that in FD SoI nMOSFET. In this paper, HC-induced device degradation is characterized under different temperatures. HCE of SLBS always has an advantage over that of SoI. The worst case bias condition for HCEs has also been studied and was found as V gs = 1/2V ds .

Bias dependence of TID radiation responses of 0.13 μm partially depleted SOI NMOSFETs

The bias dependence of total ionizing dose (TID) radiation responses of 0.13μm Partially Depleted (PD) SOI NMOSFETs is presented. Experiments and three dimensional (3D) simulations are used to analyze the buildup of trapped charge in the STI oxide as well as in the buried oxide (BOX) and its impact on the negative shift of back-gate threshold voltage and subthreshold hump. It is demonstrated that the worst-case bias conditions for the largest back-gate threshold voltage shift and increase of the off-state leakage current (or the negative shift of back-gate subthreshold hump) are different. The radiation-induced positive trapped charge in the BOX can fully deplete the body silicon for input/output (I/O) NMOSFETs as a result of the lower body doping concentration, giving rise to the coupling effect between the front-gate and back-gate threshold voltage shift.

CMOS电路总剂量效应最劣偏置甄别

CMOS电路总剂量效应最劣偏置甄别

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO 2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of the radiation response is carried out during the full manufacturing phase of the circuits.

Radiation-induced charge trapping in thin Al/sub 2/O/sub 3//SiO/sub x/N/sub y//Si(100) gate dielectric stacks

We examine the total-dose radiation response of capacitors and transistors with stacked Al/sub 2/O/sub 3/ on oxynitride gate dielectrics with Al and poly-Si gates after irradiation with 10 keV X-rays. The midgap voltage shift increases monotonically with dose and depends strongly on both Al/sub 2/O/sub 3/ and SiO/sub x/N/sub y/ thickness. The thinnest dielectrics, of most interest to industry, are extremely hard to ionizing irradiation, exhibiting only /spl sim/50 mV of shift at a total dose of 10 Mrad(SiO/sub 2/) for the worst case bias condition. Oxygen anneals are found to improve the total dose radiation response by /spl sim/50% and induce a small amount of capacitance-voltage hysteresis. Al/sub 2/O/sub 3//SiO/sub x/N/sub y/ dielectrics which receive a /spl sim/1000/spl deg/C dopant activation anneal trap /spl sim/12% more of the initial charge than films annealed at 550/spl deg/C. Charge pumping measurements show that the interface trap density decreases with dose up to 500 krad(SiO/sub 2/). This surprising result is discussed with respect to hydrogen effects in alternative dielectric materials, and may be the result of radiation-induced hydrogen passivation of some of the near-interfacial defects in these gate dielectrics.

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V GS=0 V and V GS= V DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current ( I G max ). In the case of V GS corresponding to I G max two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V GS =V GS @I G max to V GS= V DS.

Correlation between Co-60 and X-ray radiation-induced charge buildup in silicon-on-insulator buried oxides

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

Worst case total dose radiation response of 0.35 /spl mu/m SOI CMOSFETs

Through experimental results and analysis by TSUPREM4/MEDICI simulations, the worst case back gate total dose bias condition is established for body tied SOI NMOSFETs. Utilizing the worst-case bias condition, a recently proposed model that describes the back n-channel threshold voltage shift as a function of total dose, TSUPREM4/MEDICI simulations, and circuit level SPICE simulations, a methodology to model post-rad standby current is developed and presented. This methodology requires the extraction of fundamental starting material/material preparation constants, and then can be utilized to examine post-rad stand-by current at the device and circuit level as function of total dose. Good agreement between experimental results and simulations is demonstrated.

Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrier luminescence techniques

This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions.

Solution of the Two-Failure GPS RAIM Problem Under Worst-Case Bias Conditions: Parity Space Approach

With the advent of the GPS Wide Area Augmentation System (WAAS), there is increased interest in the receiver autonomous integrity monitoring (RAIM) multiple-failure problem. This paper shows how the horizontal and vertical protection level parameters (HPL and VPL) are affected by imposing a hypothetical worst-case two-failure requirement on the RAIM system. A numerical example is presented, and a short discussion of generalizing the method to more than two failures is also given. As might be expected, the paper indicates that the HPL and VPL parameters are increased significantly with the more demanding two-failure requirement as compared with detection of a single failure.

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures.

RAIM Availability for Supplemental GPS Navigation

This paper examines GPS receiver autonomous integrity monitoring (RAIM) availability for supplemental navigation based on the approximate radial-error protection (ARP) method. This method applies ceiling levels for the ARP figure of merit to screen out bad detection geometries under worst-case bias conditions. The ARP criterion value for each phase of flight is based on the integrity specifications stated in the RTCA Special Committee (SC)-159 supplemental Minimum Operational Performance Standards (MOPS) for GPS. Applying the ARP criterion, extensive analysis was performed to determine the availability of RAIM over the conterminous United States, North Atlantic, Europe, Central East Pacific, and North Pacific during en route, terminal, and nonprecision approach phases of flight. The 21 primary, optimal 21, and optimized 21 + 3 GPS constellations were examined. The results demonstrate that RAIM is not available 100 percent of the time, even with 24 operational satellites. This is because there are times when only 4 satellites are visible, preventing RAIM detection altogether, and other times when the geometry of the visible satellites has an ARP that exceeds the ARP ceiling value.

Correlation of Total Dose Damage in Capacitors and Transistors to 1.25 Micron Integrated Circuits

Parametric data taken from the irradiation of transistors and capacitors has been correlated with integrated circuit response in 1.25 micron technology. Data taken on worst case biased test transistors (+ 5 V static gate bias for n-channel, O V p-channel) accurately predicts worst case propagation delay changes in an irradiated ALU. Dynamically biased test transistors successfully model the access time delay of a RAM and a ROM after irradiation. The results indicate that worst case bias conditions for an integrated circuit during irradiation depend on the pathway measured and that test transistors provide a better measure of worst case total dose hardness of an IC rather than direct irradiation of the part itself.

Latchup in Bipolar LSI Devices

A latchup analysis procedure for four layer (pnpn) latchup is presented and applied to specific bipolar LSI devices representative of several current bipolar LSI technologies. Radiation tests were performed to verify the results of the analysis. The analysis procedure consists of a) identifying all parasitic pnpn paths on the microcircuit, b) characterizing the paths to determine if they can be latched under worst case bias conditions and c) analyzing the pnpn path within the context of the circuit to determine if latchup can be sustained under normal operating conditions. The characterization phase is further supported by analytical studies to determine what design and processing variables may be altered to insure that latchup will not occur. The results of the analysis are that a.) nonisolated I2L is immune from latchup, b.) oxide-separated technologies can easily be made immune to latchup by following certain guidelines and c.) linear compatible I2L is inherently latchup prone, even though the specific device chosen for this study did not latch under radiation.