Work Function Of Gate Electrode Research Articles

Effect of Doping Profile and the Work Function Variation on Performance of Double-gate TFET

Abstract Tunnel Field Effect Transistor (TFET) can be considered as one of the promising transistors because it can switch ON and OFF at lower voltages than the operation voltage of the metal oxide semiconductor field effect transistor (MOSFET). This paper presents the effects of gate electrode work function and the doping profile terminating within and outside the drain on the ambipolar current, the ION/IOFF ratio, and the subthreshold swing. The results show that, Gaussian doping profile terminating within the drain is the most promising for on/off ratio. All the simulations and results have been performed and obtained with the help of ATLAS device simulator (Silvaco) and MATLAB.

P‐16: Stacked PECVD SiO2 Gate Insulators for Top‐Gate Metal Oxide Thin‐Film Transistors in Enhancement Operation Mode

This work demonstrated a high‐quality type of stacked PECVD SiO2 gate insulators for top‐gate metal oxide thin‐film transistors. Moreover, together with work function of gate electrodes, their permeability for hydrogen and oxygen diffusion during post‐annealing process was adopted to effectively modulate threshold voltage, and the enhancement‐mode devices were successfully implemented.

A novel design approach of charge plasma tunnel FET for radio frequency applications

In this paper, the impact of extra electron source (EES) and dual metal gate engineering on conventional charge plasma TFET (CP-TFET) have been done for improving DC and analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET (DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit (FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance (inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET (DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally, for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES, length of drain electrode and workfunction of gate electrode 1 (GE1).

Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells

Independent-Gate (IG) FinFET is a promising device in circuit applications due to its two separated gates, which can be used independently. In this paper, we proposed a comprehensive method to optimize the Dual Threshold (DT) IG FinFET devices by carrying out modulations for the gate electrode work function, oxide thickness, and silicon body thickness. Titanium nitride (TiNx) is used as the tunable work function gate electrode for good performances. The thicknesses of the gate oxide and silicon body are swept by TCAD simulations to obtain the appropriate values. The verification simulation of the optimized transistors shows that the DT IG FinFETs can realize merging parallel and series transistors, respectively, and the current characteristics of the transistors are improved significantly. By extracting the BSIM-IMG model parameters, we can simulate the circuits composed of the proposed DT IG FinFET by using HSPICE with BSIM-IMG model. As practical examples, we optimized two novel 7T SRAM cells using DT IG FinFETs. HSPICE simulation results indicate that the new SRAM cells obtain higher write margin and read static noise margin with lower leakage power consumption than the other implementations.

Quantum analysis based extraction of frequency dependent intrinsic and extrinsic parameters for GEWE-SiNW MOSFET

This paper examines the bias-independent and bias-dependent extrinsic and intrinsic parameters of the gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) metal---oxide---semiconductor field-effect transistor (MOSFET) by considering quantum effects. The results reveal that the effect of extrinsic parameters such as the resistance, capacitance, and inductance of the electrodes is less pronounced in the GEWE-SiNW compared with the conventional SiNW or conventional MOSFET. The intrinsic transconductance of the GEWE-SiNW device can be further improved by tuning the gate metal workfunction difference, which results in shorter time constant and lower parasitic capacitance, making it suitable for radiofrequency integrated circuit (RFIC) design. It is also observed that, in the saturation region, the device exhibits improved transconductance and noticeable reduction in $$C_{\mathrm{sdx}}$$Csdx [due to drain-induced barrier lowering (DIBL)] but the parasitic capacitance and time constant also reduce. In addition, a non-quasi-static small-signal model has been studied in terms of Z and Y parameters; the results show good agreement with the results of three-dimensional (3D) simulations at thousands of GHz.

Two‐dimensional potential, electric field and drain current model of source pocket hetero gate dielectric triple work function tunnel field‐effect transistor

Low ON current and conduction for the negative gate-to-source voltage are the major drawbacks of the steep subthreshold slope tunnel field-effect transistor (TFET). Low work function on the source side of gate contact, high-κ gate dielectric and highly doped layer (delta doping) helps to enhance the ON current of the device. Whereas, low work function of gate electrode on the drain side and low-κ gate dielectric is used to eliminate the problem of conduction for the negative gate-to-source voltage. In the same concern, an analytical model for potential distribution of tri metal hetero gate dielectric delta doped TFET is developed by solving the two-dimensional (2D) Poisson's equation. Moreover, the extraction of electric field is performed by the developed potential model. However, model of drain current for the device is based on the Kane's band-to-band tunnelling generation rate. Finally, the verification of the developed model is performed with the 2D technology computer aided design ATLAS simulation results.

Pressure sensor based on MEMS nano-cantilever beam structure as a heterodielectric gate electrode of dopingless TFET

Micro-electromechanical systems (MEMS) technology has enticed numerous scientists since recent decades particularly in the field of miniaturized-sensors and actuators. Pressure sensor is pivotal component in both of the forerunning fields. The pursuance of a pressure sensor is exigently relying upon its different physical properties i.e. Piezo-resistive, Piezoelectric, Capacitive, Magnetic and Electrostatic. This article presents an outline and scrutiny of the Doping-less Cantilever Based Pressure Sensor using tunnel field effect transistor technology. The propounded pressure sensor based on the principle of capacitive gate coupling, due to which the tunneling current is modified. Additionally, to enhance the affectability of pressure sensor, the work function of metal gate electrode is amended using gas molecule diffusion. Simulation uncovers a phenomenal relationship amongst hypothetical and practical accepts of configuration. The pressure sensor is composed at Silvaco Atlas tool utilizing 40 nm technologies. The performance results exhibit that the proposed model consumes ≤1 mW power and 250 μA tunneling current per nm bending of cantilever beam structure. The inclusive length of the proposed device is 100 nm.

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (Ids) and other for cut-off frequency (fT) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of Ion/Ioff, Subthreshold Swing (SS), device efficiency, fT, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.

Study of various technological parameters on the C-Vg and the G-Vg characteristics of MOS structures

This paper was devoted to study the effects of some technological parameters (gate, oxide and doping density Na on the electrical properties of MOS structures. The conductance and capacitance were determined from a proposed admittance model. Results showed a frequency dispersion of C-Vg and G-Vg curves in inversion regime. This modeling takes into account the influence of series and parallel resistances (Rs, Rp), thickness of oxide layer, the work function of gate electrode and the doping density (Na). The C-Vg and G-Vg characteristics have been simulated at high frequency (100 kHz-1 MHz).With increasing frequency, the inversion capacitance is decreased whereas the conductance is strongly increased. A degradation of their shapes is shown in the operating accumulation and depletion modes. The accumulation capacitance seems to be strong for titanium oxide (TiO2) and for the oxide thickness is very small. Interestingly, the change of metal gate causes C-Vg shifting and variation of the values of the flat band and threshold voltages. In the inversion mode, the C - Vg and G-Vg decreases with the increase of the doping density (Na). There is a shift of the flat-band and threshold voltage (Vfb,Vth) when Na increase. Excellent agreement was observed between the calculated and the measured C-Vg curves obtained at high frequency.

Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET

This work optimizes the gate engineering scheme (both gate stack and gate metal workfunction engineering) of Stacked Gate (SG) Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire MOSFET at 300 K for improved analog and intermodulation performance. This has been done by evaluating and analyzing the metrics such as Switching Ratio, Subthreshold Swing (SS), Device Efficiency, channel and output resistance, VIP3, IIP3, 1-dB Compression Point, IMD3, HD2 and HD3. Simulation results exhibit that HfO2 as a gate stack exhibit high linearity at a comparatively low gate bias of 0.56 V with higher IIP3 (6.21 dBm) and low IMD3 (9.6 dBm). Further, the characteristics/performance is modulated by adjusting the workfunction difference of metal gate. This study demonstrates that SiNW MOSFET modeled with HfO2 as a gate stack over SiO2 interfacial layer, and gate metal workfunction difference (ΔW) of 4.4 eV can be considered as a promising potential for low power switching component in ICs and Linear RF amplifiers.

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

In this paper, we have investigated the small-signal behaviour and RF noise performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET, and the results so obtained are simultaneously compared with SiNW and conventional MOSFET at THz frequency range. This work examines reflection and transmission coefficients, noise conductance, minimum noise figure and cross-correlation factor. Results reveal significant reduction in input/output reflection coefficient and an increase in forward/reverse transmission coefficient owing to improved transconductance in GEWE-SiNW in comparison with conventional counterparts. It is also observed that minimum noise figure and noise conductance of GEWE-SiNW is reduced by 17.4 and 31.2 %, respectively, in comparison with SiNW, thus fortifying its potential application for low-noise amplifiers (LNAs) at radio frequencies. Moreover, the efficacy of gate metal workfunction engineering is also studied and the results validate that tuning of workfunction difference results further improvement in device small-signal behaviour and noise performance.

Control of Threshold Voltage for Top-Gated Ambipolar Field-Effect Transistor by Gate Buffer Layer

The threshold voltage and onset voltage for p-channel and n-channel regimes of solution-processed ambipolar organic transistors with top-gate/bottom-contact (TG/BC) geometry were effectively tuned by gate buffer layers in between the gate electrode and the dielectric. The work function of a pristine Al gate electrode (-4.1 eV) was modified by cesium carbonate and vanadium oxide to -2.1 and -5.1 eV, respectively, which could control the flat-band voltage, leading to a remarkable shift of transfer curves in both negative and positive gate voltage directions without any side effects. One important feature is that the mobility of transistors is not very sensitive to the gate buffer layer. This method is simple but useful for electronic devices where the threshold voltage should be precisely controlled, such as ambipolar circuits, memory devices, and light-emitting device applications.

Realization of Tunnel FET Operation on Junctionless FET with Single Gate Electrode Work Function

Realization of Tunnel FET Operation on Junctionless FET with Single Gate Electrode Work Function

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

In this paper, we explore the quantitative investigation of the high-frequency performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET and compared with silicon nanowire MOSFET(SiNW MOSFET) using device simulators: ATLAS and DEVEDIT 3D. Simulation results demonstrate the improved RF performance exhibited by GEWE-SiNW MOSFET over SiNW MOSFET in terms of transconductance $$(\hbox {g}_{\mathrm{m}})$$(gm), cut-off frequency $$(f_{\mathrm{T}})$$(fT), maximum oscillator frequency $$(f_{\mathrm{MAX}})$$(fMAX), power gains (Gma, G$${_\mathrm{MT}}$$MT) parasitic capacitances, stern's stability factor and intrinsic delay. Further, using three-dimensional device simulations, we have also examined the efficacy of parameter variations in terms of oxide thickness, radius of silicon nanowire, channel length and gate metal workfunction engineering on RF/microwave figure of merits of GEWE-SiNW MOSFET. Simulation result reveals significant enhancement in $$f_{\mathrm{T}}$$fT and $$f_{\mathrm{MAX}}$$fMAX; and a reduction in switching time in GEWE-SiNW MOSFET due to alleviated short channel effects, improved drain current and smaller parasitic capacitance, thus providing detailed knowledge about the device's RF performance at such aggressively scaled dimensions.

Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO2) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.

Capacitance Characteristic Optimization of Germanium MOSFETs with Aluminum Oxide by Using a Semiconductor-Device-Simulation-Based Multi-Objective Evolutionary Algorithm Method

This paper, for the first time, optimizes the characteristics of capacitance–voltage (C–V) of germanium (Ge) metal-oxide-semiconductor field effect transistors (MOSFETs) with aluminum oxide (Al2O3) by using a semiconductor-device-simulation-based multi-objective evolutionary algorithm (MOEA) technique. By solving a set of 2D semiconductor device transport equations, numerical simulation is intensively performed for the optimization of the C–V curve of Ge MOSFET devices. To optimize the capacitance of Ge MOSFETs with respect to the applied voltage, by minimizing the total errors of the C–V curve between the device simulation and a given specification (and experimentally measured data), the thicknesses of Al2O3 and GeO2, the work function of gate electrodes, the distribution range of channel doping, the dielectric constants of Al2O3 and GeO2, and the source/drain doping concentration are considered in the process of optimization. The semiconductor device simulation and the MOEA method are integrated and performed based on a unified optimization framework. According to the sharp variation characteristics of the C–V curve, except for using a residual sum of squares (RSS) (i.e., the sum of squares of residuals) as an objective function, physical key parts of the curve are also considered in the optimization problem. The engineering results of this study indicate that the semiconductor-device-simulation-based MOEA method shows great performance to optimize the parameters, which not only minimize the objective values but also match the curve shape.

High-frequency and switching performance investigations of novel lightly doped drain and source hetero-material-gate CNTFET

The effects of lightly doped drain and source (LDDS) and hetero-material-gate (HMG) structure on the static characteristics and switching speed performance for a carbon nanotube field effect transistor (CNTFET) have been theoretically investigated by a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green׳s functions (NEGF) solved self-consistently with Poisson׳s equation. A comparison study of electrical characteristics in conventional single-material-gate CNTFET (C-CNTFET), LDDS-CNTFET, HMG-CNTFET and LDDS-HMG-CNTFET structures has been performed. Simulations show that, compared with the other structures, LDDS-HMG-CNTFET significantly decreases leakage current, subthreshold swing, and increases on/off current ratio. In addition, effects of the gate electrode work function of the LDDS-HMG-CNTFET have been studied theoretically. The results indicate that the electron transport efficiency, and the cutoff frequency of the device, can be optimized by reasonably selecting the gate electrode work function. This work illustrates that the proposed LDDS-HMG-CNTFET might be useful for low-power high-speed CNTFET digital design.

Effect of Gate Electrode Work‐Function on Source Charge Injection in Electrolyte‐Gated Organic Field‐Effect Transistors

Systematic investigation of the contact resistance in electrolyte‐gated organic field‐effect transistors (OFETs) demonstrates a dependence of source charge injection versus gate electrode work function. This analysis reveals contact‐limitations at the source metal‐semiconductor interface and shows that the contact resistance increases as low work function metals are used as the gate electrode. These findings are attributed to the establishment of a built‐in potential that is high enough to prevent the Fermi‐level pinning at the metal‐organic interface. This results in an unfavorable energetic alignment of the source electrode with the valence band of the organic semiconductor. Since the operating voltage in the electrolyte‐gated devices is on the same order as the variation of the work functions, it is possible to tune the contact resistance over more than one order of magnitude by varying the gate metal.

Improvement on the electron transport efficiency of the carbon nanotube field effect transistor device by introducing heterogeneous-dual-metal-gate structure

To improve the carbon nanotube field effect transistor (CNTFET) device performance and enhance the electron transport efficiency of the device, a heterogeneous-dual-metal-gate (HDMG)-CNTFET is proposed. By appropriately modifying the transport model for single-metal-gate (SMG)-CNTFET, the electron transport properties of the HDMG-CNTFET device are investigated. The results indicate that the work function WGS of the metal gate near the source (S-gate) is fixed such that it is equal to that of the intrinsic CNT, and the work function WGd of the metal gate near the drain (D-gate) is selected to be smaller than WGS within a certain range, the electric field distribution can be optimised and the average electron velocity in the CNTFET channel can be significantly increased; at the same time, due to the electric potential modulation by the D-gate, the device has a lower threshold voltage. When the same operating voltage is applied, HDMG-CNTFET has a larger on-state current than SMG-CNTFT; and due to the shielding effect of the drain voltage variation by D-gate, the HDMG-CNTFET device exhibits good gate-control ability and can suppress the drain-induced barrier lower effect, hot electron effect and ambipolar conduction behavior compared with SMG-CNTFET. This study, by reasonably selecting the gate electrode work function of the HDMG-CNTFET, can effectively overcome the deficiency of existing research on improving the CNTFET performance at the expense of reducing the on-current, more importantly, can improve the electron transport efficiency, thereby improving the characteristic frequency and reducing the delay time of the device, which will be of benefit to CNTFET application in high-speed/high-frequency circuit.

Effect of gate electrode work function in conventional and junctionless FinFETs

This paper investigates the effect of gate electrode work function in 30 nm gate length conventional and junctionless FinFETs using technology computer-aided design (TCAD)simulations. DC parameters, threshold voltage (vt), drive current (Ion) and output resistance (Ro), and RF parameters, unity gain cut-off frequency (ft), non-quasi static (NQS) delay and input impedance (Z11) are investigated. Junctionless devices being bulk conductive behaves differently with respect to work function variation compared to surface conducting conventional devices. The rate of change in Vt and Ion with respect to work function, in junctionless devices, is slower compared to conventional devices. Owing to better drain induced barrier lowering (DIBL) performance, junctionless devices have higher output resistance. In conventional devices, ft is not sensitive for most of the work function range due to the screening effect of the inversion layer whereas junctionless device shows strong dependency on the work function. Key words: FinFET, Junctionless transistor, work function, drain induced barrier lowering (DIBL), technology computer-aided design (TCAD).