Word Line Research Articles

Mitigating Pass Gate Effect in Buried Channel Array Transistors Through Buried Oxide Integration: Addressing Interference Phenomenon Between Word Lines

As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cycles, causing performance degradation. Specifically, in the 6F2 DRAM structure, activating a word line (WL) lowers the energy barrier of adjacent WLs, leading to the Pass Gate Effect (PGE). This study investigates the use of buried oxide beneath the WL to mitigate the PGE through simulation. Using SILVACO TCAD, we analyzed the impact of varying the size and position of the buried oxide on the PGE. The results showed that increasing the oxide size or reducing the distance to the WL effectively reduced the PGE. However, the presence of interface traps, which increase with the addition of buried oxide, was found to exacerbate the PGE, indicating that minimizing interface traps is crucial when incorporating buried oxide.

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Innovative Programming Approaches to Address Z-Interference in High-Density 3D NAND Flash Memory

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory.

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

A Common Source 3D FeFET with Disturb Inhibition Program and Erase Method

A common source p-type single-crystal channel three-dimensional ferroelectric field-effect transistor (3D FeFET) in a 2 × 2 × 3 array is proposed. Two programming and erasing conditions are introduced. A large memory window (>1.2 V), good retention (>10 years), and high speed (<100 ns) was presented under high voltage (±6 V) conditions. The endurance, >103, was observed under relatively low voltage (±3 V) conditions. Based on these two conditions, a novel asymmetric bias program and erase method is proposed to obtain good disturb inhibition. A more than 0.5 V threshold voltage shift in target cell was achieved while threshold voltage shift in unselected cell was limited, and analysis of long term disturb in novel method is proposed, showing good disturb inhibition. Additional investigation in word line disturbance shows causation and efficiency of disturb. Building upon the proposed structure of the 3D FeFET array, a vector matrix multiplication able to calculate 2-bit weights was designed and demonstrated. This work provides a potential solution for increasing integration density with 3D FeFET array.

Realization of skyrmion shift register

The big data explosion demands novel data storage technology. Among many different approaches, solitonic racetrack memory devices hold great promise for accommodating nonvolatile and low-power functionalities. As representative topological solitons, magnetic skyrmions are envisioned as potential information carriers for efficient information processing. While their advantages as memory and logic elements have been vastly exploited from theoretical perspectives, the corresponding experimental efforts are rather limited. These challenges, which are key to versatile skyrmionic devices, will be studied in this work. Through patterning concaved surface topography with designed arrays of indentations on standard Si/SiO2 substrates, we demonstrate that the resultant non-flat energy landscape could lead to the formation of hexagonal and square skyrmion lattices in Ta/CoFeB/MgO multilayers. Based on these films, one-dimensional racetrack devices are subsequently fabricated, in which a long-distance deterministic shifting of skyrmions between neighboring indentations is achieved at room temperature. Through separating the word line and the bit line, a prototype shift register device, which can sequentially generate and precisely shift complex skyrmionic data strings, is presented. The deterministic writing and long-distance shifting of skyrmionic bits can find potential applications in transformative skyrmionic memory, logic as well as the in-memory computing devices.

Improvement of warpage and leakage for 3D NAND flash memory

GLS (Gate line split) filling is a very important process in 3D NAND flash memory (3D NAND) fabrication. Filling materials in the GLS should have threefold properties, such as warpage tunability, leakage-free and low resistance. In this paper, the effects of different GLS filling materials (SiO2, W, amorphous silicon: A-Si) on F-attack, warpage and resistance were studied. GLS filled with A-Si shows best performance on warpage and F-attack. For 3D NAND, the number of stacked layers is predicted as a function of the wafer warpage, and the wafer warpage difference between GLS filled with A-Si and W was compared. With the same number of stacking layers, the wafer warpage post GLS filled with A-Si is smaller than that filled with W. Meanwhile, A-Si is produced by the decomposition of SiH4 by low pressure chemical vapor deposition (LPCVD) process, F-related by-product in the GLS filling material and consequent ACS (array common source) to WL (Word line) leakage by F-attack are avoided. A-Si is the best choice for GLS filling. This work provides an efficient method to solve the warpage and leakage problem in 3D NAND flash memory fabrication.

An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal–Ferroelectric–Insulator–Silicon (MFIS) capacitor utilizing Hafnium–Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (Vpass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach Vpass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (Vth) shift of the selected cell and the pass disturb of the unselected cells according to the Vpass condition were analyzed. Consequently, there was a more significant change in Vth among selected cells compared to the time for unselected cells to reach Vpass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of Vth according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

Improvement of fluorine attack induced word-line leakage in 3D NAND flash memory

In this work, the influence of fluorine (F) erosion on tungsten (W) gate process is studied, and the measure to mitigate the word line (WL) leakage resulting from F erosion in 3D NAND flash memory is proposed. As the number of layers in 3D NAND increases, the tungsten (W) gate word line (WL) layer fill process becomes more challenging in the post-gate process. As the fill path length increases, the tungsten gates become more susceptible to voiding during deposition, resulting in the accumulation of fluorine (F) by-products, and causing fluorine attack issues. In particular, under the influence of subsequent high-temperature processes, the by-products containing fluorine can diffuse into the surrounding structure and corrode the surrounding oxide layer. This leads to WL leakage, thereby affecting device yield and reliability. This paper begins by analyzing the microscopic principles of fluorine erosion in 3D NAND. We also propose a low-pressure annealing method to address the issue of fluorine erosion. Then, we conduct the experiments on annealing planar thin film stacks and 3D filled structures under atmospheric condition and low-pressure condition. We use various methods to characterize the concentration and distribution of residual fluorine elements. The experimental results demonstrate that under appropriate conditions, the residual fluorine in the tungsten gate can be effectively released by low-pressure annealing, thus reducing the leakage index of the word line. Additionally, as the outer CH is closer to the fluorine discharge channel, the influence of low-pressure annealing on the outer CH is more pronounced than on the inner CH. The low-pressure annealing can significantly reduce the fluorine content in the tungsten gate. This method can also mitigate the issue of fluorine attack oxides and reducethe WL leakage. Using low-pressure annealing treatment can also enhance the quality of 3D NAND flash technology.

First-principles study of F adsorption by TiN with its oxide surface in three-dimensional NAND flash memory

Three-dimensional (3D) NAND flash memory is a key technology in the field of mainstream memory solutions, which is primarily due to its extremely low bit cost. The architecture of 3D NAND, characterized by its vertically stacked design, substantially enhances the capacity of individual chips. This advancement is completely consistent with the demands for high-capacity data storage in contemporary environments, securing its widespread adoption in diverse application scenarios. As storage density increases, the complexity of process integration increases, bringing new challenges. The word lines in 3D NAND are typically filled by using gate replacement techniques, and compared with chemical vapor deposition (CVD), atomic layer deposition (ALD) is favored for its superior step-coverage, especially for depositing tungsten (W) at the gate. However, due to the complexity of the replacement gate deposition structure, fluorine (F) residues are found in the voids of the tungsten metal gate filling structure and diffuse into the surrounding structure under subsequent process conditions, corroding other films such as silicon oxide and degrading device performance and reliability. To alleviate the problem of fluorine attack, a thin layer of titanium nitride is usually deposited as a barrier layer before deposition of tungsten gate, which blocks the fluorine in the tungsten gate and prevents its diffusion into the oxide layer. Previously, there were studies to increase the ability to stop F diffusion by varying the thickness of the F blocking layer (TiN). However, increasing the thickness of TiN will further increase the complexity of high aspect ratio etching in the 3D NAND process, which will have adverse effect on subsequent processes. To further minimize the effect of fluorine erosion, residual fluorine elements can be removed by introducing annealing in the subsequent process flow. In the actual 3D NAND process, elemental fluorine (F) is adsorbed and accumulates on the TiN surface, and is further activated by subsequent high-temperature processes, leading to severe fluorine erosion. The delay between TiN deposition and subsequent processing steps is hypothesized to facilitate fluorine adsorption due to the oxidation of TiN. This work corroborates this hypothesis through first-principles calculations, and demonstrates the role of TiN oxidation in fluorine adsorption. In this work, we evaluate the effect of this oxidation on the fluorine-blocking effectiveness of the TiN barrier layer. We simulate the adsorption of fluorine-containing by-products on TiN and its oxides, providing theoretical insights into mitigating fluorine attack. The higher degree of oxidation of TiN is more likely to cause F adsorption, and Ti exposed surface TiN is more prone to oxidation, which is more likely to cause F adsorption in unoxidized condition and oxidized condition. Based on these insights, we implemente an ammonia purge treatment in 3D NAND manufacturing, which effectively minimizes fluorine attack, reducing the leakage probability of word line by 25% and wafer warpage by 43%.

3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure

The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR).In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells.It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1

Spatiotemporal Data Processing with Memristor Crossbar-Array-Based Graph Reservoir.

Memristor-based physical reservoir computing (RC) is a robust framework for processing complex spatiotemporal data parallelly. However, conventional memristor-based reservoirs cannot capture the spatial relationship between the time-varying inputs due to the specific mapping scheme assigning one input signal to one memristor conductance. Here, a physical "graph reservoir" is introduced using a metal cell at the diagonal-crossbar array (mCBA) with dynamic self-rectifying memristors. Input and inverted input signals are applied to the word and bit lines of the mCBA, respectively, storing the correlation information between input signals in the memristors. In this way, the mCBA graph reservoirs can map the spatiotemporal correlation of the input data in a high-dimensional feature space. The high-dimensional mapping characteristics of the graph reservoir achieve notable results, including a normalized root-mean-square error of 0.09 in Mackey-Glass time series prediction, a 97.21% accuracy in MNIST recognition, and an 80.0% diagnostic accuracy in human connectome classification.

-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design

Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used for energy-saving and stable use. To speed up the writing process of the design, a single transistor is inserted between the cross-coupled inverters. In addition, to increase the node capacity, the voltage boosting circuitry is emphasized. The adaptive word line control scheme was utilized by integrating the replica column based circuit. The Replica approach regulates signal flow through the core by using a dummy column and a dummy row in RAM. To demonstrate the viability of the suggested design, the simulated outcomes are contrasted with those of existing designs. The various performance metrics examined are Read Static Noise Margin (RSNM), Write (WSNM), Hold (HSNM), Read Access Delay (RAD), Write Access Delay (WAD), Read performance and Write performance the varying supply voltage is evaluated.

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit

Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.

A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch

This paper presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multiply-and-accumulate (MAC). The columnsensing dual-phase 6b successive-approximation-register (SAR) analog-to-digital-converter (ADC) maximizes the through-put with minimized pitch. The proposed CIM occupies an active area of 0.0155mm2 and consumes 4.36mW with an average energy efficiency of 25.8TOPS/W. The measured performance achieves the highest normalized throughput with an end-to-end inference accuracy comparable to FP32 with less than a 0.11% drop.

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

Word and bit line operation of a 1 × 1 μm2 superconducting vortex-based memory

The lack of dense random access memory is one of the main bottlenecks for the creation of a digital superconducting computer. In this work we study experimentally vortex-based superconducting memory cells. Three main results are obtained. First, we test scalability and demonstrate that the cells can be straightforwardly miniaturized to submicron sizes. Second, we emphasize the importance of conscious geometrical engineering. In the studied devices we introduce an asymmetric easy track for vortex motion and show that it enables a controllable manipulation of vortex states. Finally, we perform a detailed analysis of word and bit line operation of a 1 × 1 μm2 cell. High-endurance, non-volatile operation at zero magnetic field is reported. Remarkably, we observe that the combined word and bit line threshold current is significantly reduced compared to the bare word-line operation. This could greatly improve the selectivity of individual cell addressing in a multi-cell RAM. The achieved one square micron area is an important milestone and a significant step forward towards creation of a dense cryogenic memory.

Radiation hardened 11T memory cell for space applications

Continuous nanometer technology scaling, along with rapid growth in the field of artificial intelligence (AI), internet-of-things (IoT), and other high-performance computing applications increases the need for low power and soft error immune VLSI circuits. Conventional radiation hardened bit cell such as QUATRO10T with partial single event upset (SEU) immunity and bit cells such as DICE12T, WE-QUATRO12T, and RHD13T needs large area and power consumption. To address these problems, a soft error immune radiation hardened memory cell 11T (RHMC11T) static random-access memory (SRAM) bit cell is proposed which is immune to both SEU and single event multiple node upsets (SEMNU) along with good read and write stability. The enhancement in the key parameters of the proposed cell is confirmed by comparing the proposed bit cell with the conventional bit cells such as 6T, NS10T, PS10T, QUATRO10T, RHMD10T, RHBD10T, 11T, and 12T. The critical charge of the proposed RHMC11T is improved by 43%, 27%, 19%, 2%, 2%, and 4% while comparing with 6T, NS10T, PS10T, QUATRO10T, RHBD10T, and 11T. The proposed bit cell has higher SVNM of 49%, 19%, 11%, 8%, and 5% and smaller WTV of 50%, 33%, 23%, 18%, and 21% compared to 6T, PS10T, RHMD10T, RHBD10T, and 12T respectively. The proposed RHMC11T has lesser read access time of 63%, 50%, 46%, 6%, and 6% compared to NS10T, PS10T, QUATRO10T, RHMD10T, and 11T. The proposed RHMC11T bit cell with dedicated write and read word lines makes it applicable for bit interleaving architecture and also it satisfies reliability requirements making it a good choice for highly radiative terrestrial environment applications such as in aerospace and satellites.