A Common Source 3D FeFET with Disturb Inhibition Program and Erase Method

Abstract

A common source p-type single-crystal channel three-dimensional ferroelectric field-effect transistor (3D FeFET) in a 2 × 2 × 3 array is proposed. Two programming and erasing conditions are introduced. A large memory window (>1.2 V), good retention (>10 years), and high speed (<100 ns) was presented under high voltage (±6 V) conditions. The endurance, >103, was observed under relatively low voltage (±3 V) conditions. Based on these two conditions, a novel asymmetric bias program and erase method is proposed to obtain good disturb inhibition. A more than 0.5 V threshold voltage shift in target cell was achieved while threshold voltage shift in unselected cell was limited, and analysis of long term disturb in novel method is proposed, showing good disturb inhibition. Additional investigation in word line disturbance shows causation and efficiency of disturb. Building upon the proposed structure of the 3D FeFET array, a vector matrix multiplication able to calculate 2-bit weights was designed and demonstrated. This work provides a potential solution for increasing integration density with 3D FeFET array.