Word-line Voltage Research Articles

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (Vpass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach Vpass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (Vth) shift of the selected cell and the pass disturb of the unselected cells according to the Vpass condition were analyzed. Consequently, there was a more significant change in Vth among selected cells compared to the time for unselected cells to reach Vpass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of Vth according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively.At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05 V when the Vt variability (= -6σ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μW at VDD = 1.0 V, which was 9.46% of PST of the conv SRAM (10.12 μW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

Area and Energy Efficient SOT-MRAM Bit Cell Based on 3 Transistors With Shared Diffusion Regions

In this paper, we present a novel bit cell structure of spin-orbit-torque magnetic random access memory (SOT-MRAM) for the reduction of both cell size and write energy consumption. Based on the shared diffusion region architecture, all of the 3 transistors in one SOT-MRAM bit cell contribute to supply driving current for deterministic write operations. Implemented with a 40 nm CMOS technology, the proposed design achieves cell area reduction of 32% compared to conventional 2-transistors-based bit cell design from the simulation result. In addition, word-line voltage for access transistors in both designs are optimized and compared. Write energy of the proposed bit cell decreases with proper word-line voltage of the access transistors, reaching 80% (92%) write-P (AP) of the conventional cell design. Both the cell size scaling and energy saving make the proposed bit cell a viable design for high density and energy efficient SOT-MRAM.

Edge Word-Line Reliability Problem in 3-D NAND Flash Memory: Observations, Analysis, and Solutions

The 3-D flash memory is gradually becoming the mainstream nonvolatile storage medium due to its high capacity and high performance. However, interlayer interference during 3-D flash programming leads to significant differences in the error characteristics of edge and inner word lines; interlayer interference becomes more pronounced as the number of stacked layers increases, seriously affecting data storage reliability. In this study, many actual tests were conducted on triple-level cell (TLC) and quad-level cell (QLC) flash memory, which are the mainstream storage media in the current consumer market, to obtain the edge and inner word-line threshold voltage data under the interference of different factors, such as retention loss and read disturb; then, the threshold voltage difference between the edge and inner word lines under different conditions was quantitatively analyzed. An edge word-line reliability optimization strategy is proposed based on the read-reference voltage extra offset (RRVEO). Experimental results show that this strategy can reduce the edge word-line raw bit error rate (RBER) by more than 90% and eliminate the reliability difference between inner and edge word lines without significant overhead, thus significantly improving the data storage reliability of flash memory.

An Implantable Bio-Signal Sensor SoC with Low-Standby-Power 8K-Bit SRAM for Continuous Long-Term Monitoring

Individualized treatment of chronic diseases opens up great opportunities for implantable biosensor systems capable of tracking vital signals over long periods of time. To this end, low-power techniques in standby mode and the efficient utilization of storage space will be important issues for the implementation of such rechargeable implants with a built-in memory. This paper presents key circuit techniques, including a leakage-current-based clock generator that eliminates the need for an internal reference clock source, a low-standby-power 8Kbit SRAM with negative wordline and dynamic supply voltage scaling, and an adaptive sensing scheme to improve storage space utilization. When implemented with commercial 180 nm CMOS technology for the circuit simulation, approximately 70% (100 nW) of power dissipation was reduced from internal clock source, about 70% of power consumed by 8Kbit SRAM was saved, and the storage space utilization was improved by about 42.8%. In the end, the proposed implantable biosensor SoC consumes about 82.5 nW of standby power, saving about 42% from the previous approach and can last for 2.5 days using a 5 uAh thin-film battery (CYMBET® 1.7 × 2.2 mm2).

Performance estimation of non-hysteretic negative capacitance FinFET based SRAM

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14 nm conventional FinFET to form NC-FinFET. Static and dynamic behavior of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET based SRAM, 6T-NCSRAM exhibits distinct behavior during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltage-generating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5V to 2.1V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3mV at 30pF load with 20MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7ns, even though the average standby current is less than 0.98µA typically.

Design of auto-store circuit for nvSRAM with SONOS access transistor

In this paper, an auto-store circuit that can perform a store and restore operation of non-volatile SRAM (nvSRAM) with access transistor whose gate stack is Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is designed. The suggested auto-store circuit is consisted by two small circuit parts of a store and restore circuit. The store circuit moves data in SRAM cell into SONOS device before power turns off while a restore circuit recalls the data to SRAM cell when the power is resupplied. When the nvSRAM replaces its conventional access transistor with the SONOS flash memory device, higher word line voltage is needed for a store operation. It demands much energy and additional voltage source to store a data. To overcome this disadvantage, the capacitor component is added in the store and restore circuit which is charged during the normal operation mode. At the moment of the power-off, the store circuit discharges the capacitors and applies higher voltage to the word line for the store operation. When the power is supplied again, the restore circuit discharges the capacitor and applies pre-charge voltage and restore the data to the bit line and word line. The simulation results show that the suggested auto store circuit can perform the store, restore operation in the sudden power off without an additional voltage source.

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit.

Hardware-Robust In-RRAM-Computing for Object Detection

In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware. Although previous approaches including these effects in model training successfully improved variation tolerance, they only considered part of the nonideal effects and relatively simple classification tasks. This paper proposes a joint hardware and software optimization strategy to design a hardware-robust IRC macro for object detection. We lower the cell current by using a low word-line voltage to enable a complete convolution calculation in one operation that minimizes the impact of nonlinear addition. We also implement ternary weight mapping and remove batch normalization for better tolerance against device variation, sense amplifier variation, and IR drop problem. An extra bias is included to overcome the limitation of the current sensing range. The proposed approach has been successfully applied to a complex object detection task with only 3.85\% mAP drop, whereas a naive design suffers catastrophic failure under these nonideal effects.

Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD

A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated. In particular, a capture cross-section (CCS) value that is far from the real value is used. Furthermore, it does not consider the latest device structure and its operation. In this paper, a conventional GIDL-assisted erase compact model is validated using TCAD and has been improved more practically. It is confirmed that we should distinguish between CCS in TCAD and the compact model due to their differences. Based on their physical differences, an equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering a tapered angle, single-side injection and word-line voltage is suggested.

A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic

We present an embedded memory for possible neuromorphic computing applications using a via-type resistive random access memory (RRAM) gated metal-oxide semiconductor field-effect transistor (MOSFET). By this arrangement, the threshold voltage (V th) of the MOSFET is modulated by the resistance of the via-type RRAM. When the resistance of the via-type RRAM is in a high-resistance state (HRS), the word-line voltage (V WL) is consumed mostly across the via-type RRAM and little is left on the gate dielectric layer of the MOSFET; the V th of the MOSFET is boosted. In contrast, when the resistance of the via-type RRAM is in a low-resistance state (LRS), with the resistance value much smaller than that of the gate dielectric of the MOSFET, the VWL will be dropped majorly on the gate dielectric of the MOSFET, and the V th of the MOSFET will be much reduced than that of the MOSFET gated by the via-type RRAM in a HRS. The experimental results show that, in a direct-current mode, the memory window achieves 1 V between a LRS and a HRS of the via-type RRAM gated MOSFET. In an alternating current mode, the LRS can be SET at 10 nanoseconds; the HRS can be RESET at 5 nanoseconds. Furthermore, three-bit-per-cell operation of the via-type RRAM gated MOSFET is demonstrated. The eight conductance states are distributed evenly between 100 micro- and 100 picosiemens with almost isometric gaps in between. The endurance tests were executed for eight conductance states with one million cycles for four pairs. Finally, the retention tests of eight states were kept under 125 °C for one month.

A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of threshold voltage of the memory cells and the efficiency can be improved to save power consumption at the same time. What is more, with the minimized ripple, the requirement for power supply rejection ratio (PSRR) of the high-voltage regulator used to provide low noise WL voltage can be reduced. The proposed WL voltage generator has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> triple-well CMOS process and the core chip size is 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . While operating at a 1.8-V supply, the measurement results show that the ripple voltage is 5.5 mV at 12-V output voltage under the typical 50-pF cap load conditions of 3-D NAND Flash memories. Furthermore, the output ripple hardly varies with the increase of load current. In addition, the maximum power efficiency is 49% at 400 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and can be maintained over 30% in the 50–450- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> current load range.

Design of Low Power and Failure Free SRAM Cell Using Read Assist Circuits

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.

Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a 0.18 μm BCD process, and the effective chip area is 2.4mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What's more, the maximum peak current is reduced by 35%.

A Small Ripple Program Voltage Generator Without High-Voltage Regulator for 3D NAND Flash

This brief presents a programmable voltage generator with the scheme of separated dynamic clock voltage scaling for program operation in 3D NAND flash memories, where the ripple of program voltage can be minimized to reduce the variation of threshold voltage of the programmed cells. The proposed scheme drastically reduces the output ripple and improves the loop stability at the same time. What’s more, the high voltage regulator used in the conventional wordline voltage generator is not necessary anymore. The proposed generator has been implemented in a 0.18 $\mu \text{m}$ triple-well CMOS process, and the effective chip area is 0.55 mm2. Under the equivalent load conditions of 3D NAND flash, the measurement results show that the maximum ripple voltage is 2.06 mV, and the ripple is independent from clock frequency and output voltage. Moreover, the peak efficiency is about 36% at 23 V output voltage.

Effect of OFF-state stress on reliability of nMOSFET in SWD circuits of DRAM

In this paper, we investigate the effect of OFF-State stress occurring at nMOSFET in a sub word-line driver (SWD) circuit under the DRAM operating conditions. Through the experimental study, we found that the increase in the number of OFF-carriers by the OFF-State stress caused the significant decrease of ON-current (Ion). During the initial period, the OFF-State stress generated the positive oxide charges (Qox) and the interface traps (Nit), which caused the increase of OFF-current (Ioff) and the decrease of Ion. After the degradations were saturated, both the Ion and Ioff decreased due to the increase in the number of OFF-carriers. Also the OFF-State degradation increased with decreasing source voltage, channel doping concentration, and channel length. Furthermore, the sensitivity of the OFF-State degradation to body bias (Vb) increased with scaling the oxide thickness (Tox). These new observations suggest that the OFF-State degradation for core transistors can impose the significant limitation on the SWD circuit design in DRAM such as scaling of dimension and determination of word-line voltage.

Static noise margin trade-offs for 6T-SRAM cell sizing in 28 nm UTBB FD-SOI CMOS technology

In this paper, analytical expressions for the conventional definition of write static noise margin (WSNM) for 6T-SRAM cells at sub-threshold operation are derived. Drain-induced barrier lowering (DIBL) and body-biasing effects are considered in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. By observing the expressions for WSNM and read SNM (RSNM) we introduce an alternative design parameter (Γ) for 6T-SRAM cell sizing, whose purpose is to control read and write static noise margins simultaneously, thereby providing effective stability balance. This paper also shows that low-leakage cells with suitable stability can be designed by using a non-traditional sizing for 6T-SRAM cells, in which increased transistor lengths are employed to reduce leakage, assisted by a word-line voltage reduction technique to increase read margin. In addition, a statistical analysis for both read and write static noise margins taking into account manufacturing process variations was carried out with the purpose of designing a high-yield 6T cell. Analytical expressions and the designed 6T cell were verified by extensive HSPICE simulations using a 28 nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.

A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM

A readout circuit with slew rate compensation for nano-scaled SRAMs (Static Random-Access Memory) is proposed in this study. Since the leakage current will dramatically increase to jeopardize memory read/write performance when the nano-scaled SRAM is operated at high system voltages, the proposed AVD (Adaptive Voltage Detector) is utilized to detect the system voltage variation to resolve this issue. When AVD generates an enable signal to WLBC (Word Line Boost Circuit), WLBC will boost wordline voltage to drive the SRAM cell such that the output slew rate is increased. Therefore, the active power of the SRAM will be reduced. A prototypical SRAM is implemented using TSMC 28 nm CMOS logic low power technology. By measurement results at 0.8 V system voltage, the proposed compensation design reduces 17.2% of the power dissipation, and enhances the output slew rate by 46.5% at the expense of 6.6% area overhead. The energy per access is measured to be 0.414 pJ given a 0.8 V system voltage and 100 MHz system clock.

Design of Sram Architecture with Low Power without Affecting Speed Using Finfet

Abstract In average 8T SRAM Architecture, it requires maximum number of transistor counts and does not need any write back scheme. To achieve the higher word line (WL) Voltage, the bit line (BL) is connected to the gate of the read buffer SRAM Architecture. That boosted voltage is not used when the threshold voltage is high. Its leads to the reduction of read stability of the SRAM Design. In that case, the gate terminal of the SRAM Architecture is not connected to the buffer results a large delay. To overcome the disadvantage of the average 8T SRAM architecture, the 6T SRAM Design is proposed. In proposed 6T SRAM Design, the number of transistor counts and Power is reduced than the existing design. Various factors of the proposed SRAM Architecture, which stores multiple bits in terms of power and transistor counts. The simulation of 6T SRAM design is carried out in S-Edit and the synthesized in T-Spice.