Area and Energy Efficient SOT-MRAM Bit Cell Based on 3 Transistors With Shared Diffusion Regions

Abstract

In this paper, we present a novel bit cell structure of spin-orbit-torque magnetic random access memory (SOT-MRAM) for the reduction of both cell size and write energy consumption. Based on the shared diffusion region architecture, all of the 3 transistors in one SOT-MRAM bit cell contribute to supply driving current for deterministic write operations. Implemented with a 40 nm CMOS technology, the proposed design achieves cell area reduction of 32% compared to conventional 2-transistors-based bit cell design from the simulation result. In addition, word-line voltage for access transistors in both designs are optimized and compared. Write energy of the proposed bit cell decreases with proper word-line voltage of the access transistors, reaching 80% (92%) write-P (AP) of the conventional cell design. Both the cell size scaling and energy saving make the proposed bit cell a viable design for high density and energy efficient SOT-MRAM.