Word Bit Research Articles

In‐Depth Analysis of One Selector–One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance

This work provides a comprehensive analytical analysis of one‐selector‐one‐resistor (1S1R) crossbar array (CBA) device for hardware neural network (HNN) applications. Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the V/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size N of the CBA, where N indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large N value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply‐and‐accumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on‐state conductance increases the available N value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.

Design and implementation of Dual-Port Memory

Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.

Low power SRAM using Adiabatic Logic

In this paper the design of low power SRAM has been presented. SRAM memory cell has been realized using adiabatic logic to achieve low power operation. Adiabatic SRAM has been realized using two methods such as i) gradual charging and discharging of bit-line during writing mode and ii) utilizing control transistor based adiabatic circuit i.e., Two Phase Adiabatic Dynamic Logic (2PADL) circuit for the design of memory cell. Furthermore, energy recovery of word line and bit line charge stored in the interconnect capacitances has been realized for the benefit of energy savings. Charge recovery circuits based on 2PADL has been employed in the proposed SRAM memory core to achieve energy recovery. SRAM memory array of (4×4) has been designed as a test circuit. All the circuits are implemented using 180nm CMOS technology and simulations are carried out using Cadence® Virtuoso tool. Simulation results prove that the proposed memory cell has significant amount of energy savings when compared to the conventional static CMOS SRAM cell.

MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computation cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed at the crossbar array and the limited capacity of CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computation costs, network pruning and quantization are two widely studied compression methods to shrink the model size. However, most of the model compression algorithms can only be implemented in digital-based CNN accelerators. For implementation in a static random access memory (SRAM) CIM-based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros, such as the number of word lines and bit lines that can be turned on at the same time, as well as how to map the weight to the SRAM CIM macro. In this study, a software and hardware co-design approach is proposed to design an SRAM CIM-based CNN accelerator and an SRAM CIM-aware model compression algorithm. To lessen the high-precision MAC required by batch normalization (BN), a quantization algorithm that can fuse BN into the weights is proposed. Furthermore, to reduce the number of network parameters, a sparsity algorithm that considers a CIM architecture is proposed. Last, MARS, a CIM-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparsity neural network, is proposed.

Signal Integrity Design and Analysis of 3-D X-Point Memory Considering Crosstalk and IR Drop for Higher Performance Computing

In this article, we, for the first time, used signal integrity (SI) to design and analyze 3-D X-Point memory, including a phase-change memory (PCM) cell, ovonic threshold switch (OTS) selector, interconnection lines, and peripheral circuits. With the narrow space and the long interconnection lines that come with 20-nm process technology, crosstalk and IR drop can degrade the voltage margin of the memory cell and affect the memory operation. For SI analysis considering crosstalk and IR drop, the unit size of the memory array tile was considered in designing the interconnection lines. Crosstalk and IR drop are analyzed using full 3-D electromagnetic and circuit simulations. To cover practical conditions, the PCM cell and OTS selector are modeled as behavior models using Verilog-A modules, respectively. Also, the word lines (WLs) and bit lines (BLs) of 3-D X-Point memory are modeled to resistance and capacitance by ANSYS Q3D extractor. The core peripheral circuits, such as decoder, sense amplifier, and analog-to-digital converter, are included in the circuit simulation. To verify the proposed design and analysis, a transient simulation was conducted considering crosstalk and IR drop of 3-D X-Point memory. A tradeoff relationship between crosstalk and IR drop in the interconnection designs was verified. Additionally, to suppress crosstalk and reduce IR drop, the new design of the interconnection lines considering the tradeoff between SI issues is proposed. The newly proposed interconnection design shows 30% improvement in the voltage margin considering the IR drop issues and under 10% enhancement of crosstalk noise. It is expected that the SI analysis and design methodologies could be widely applied in other new memory developments.

Design of Distributed Protograph LDPC Codes for Multi-Relay Coded-Cooperative Networks

This paper studies protograph low-density parity-check coded cooperation (CC) schemes for two-hop multi-relay systems with $L$ relays over Nakagami- $m$ quasi-static fading (QSF) channels. We propose two CC schemes, namely schemes I and II, with different maximum code rates to satisfy different transmission requirements. We further design a family of distributed rate-compatible root-protograph (RCRP) codes to achieve full diversity in CC-based multi-relay QSF channels. In particular, our RCRP codes with $L+1$ sub-codewords can realize full diversity in scheme I, and our RCRP codes with two sub-codewords can achieve full diversity in scheme II with a maximum-ratio combiner. In addition, we estimate the asymptotic word error rate and bit error rate of our RCRP codes using a generalized protograph extrinsic information transfer algorithm, which is able to characterize the error performance of finite-length codewords accurately. Analysis and simulation show that our RCRP codes can achieve outage-limit-approaching performance in both multi-relay CC architectures. This makes the RCRP coding framework extremely attractive for multi-relay cooperative communication applications with slow-varying fading.

Read margin analysis of crossbar arrays using the cell-variability-aware simulation method

This paper proposes a new concept of read margin analysis of crossbar arrays using cell-variability-aware simulation. The size of the crossbar array should be considered to predict the read margin characteristic of the crossbar array because the read margin depends on the number of word lines and bit lines. However, an excessively high-CPU time is required to simulate large arrays using a commercial circuit simulator. A variability-aware MATLAB simulator that considers independent variability sources is developed to analyze the characteristics of the read margin according to the array size. The developed MATLAB simulator provides an effective method for reducing the simulation time while maintaining the accuracy of the read margin estimation in the crossbar array. The simulation is also highly efficient in analyzing the characteristic of the crossbar memory array considering the statistical variations in the cell characteristics.

A new bias scheme for a low power consumption ReRAM crossbar array

This paper proposes a new bias scheme for a crossbar array that can improve the power consumption and read margin. The concept of the newly proposed 5/12 bias scheme is to reduce the bias of the unselected cells for power consumption and the bias of half-selected cells for a reduced line voltage drop of the selected cell. In the 5/12 bias scheme, the unselected word line and bit line are biased to 5 × Vapp/12 and 7 × Vapp/12, respectively. The electrical characteristics of the 5/12 bias scheme are evaluated by HSPICE simulations and it is found that appropriate nonlinearity of selector can simultaneously achieve low power consumption and high read margin for 5/12 bias scheme.

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a hierarchical verification technique is used for macro design; all the interconnection wires needed to generate a RAM/ROM macro are installed in each physical leaf cell by way of preparation. The macro size is configurable regarding both word count and bit width. Moreover, back annotations after generating a macro are not necessary because there are no unknown factors such as parasitic resistance and/or capacitance. To reduce the power consumption of RAM/ROM macros, six narrow-channel MOSFETs (two pMOSs and four nMOSs) are prepared in the base cell, resulting in a new 10-transistor-type base cell. Using one single base cell, we can implement an SRAM cell (up to two ports), a 4-bit ROM cell, or a 2-input logic gate. When designing the ROM cell, we adopt a double-rail bitline scheme to shorten the bitline delay. Another high-speed technique is to use a new current-mirror sense amplifier. Owing to the high sensitivity (47 mV) of this amplifier, we have successfully reduced the required read bitline signal from 300 to 100 mVpp. With regards to layout techniques, we propose a new high-density address decoder using a subdecoder and complex logic gates. In addition, some verification techniques using phantom base cells are devised. These techniques are confirmed with a gate-array RAM/ROM macro test chip fabricated with a 0.6- $\mu \text{m}$ low cost, CMOS process. With a two-port SRAM with 256 cells/bitline, the address access time under typical conditions of 3.3 V and 25 °C is 7.125 ns and the power-supply current at a 40-MHz operation is 3.8 mA for an I/O-data width of 1 bit.

A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays

In this article, an alternative approach to SRAM testing – the dynamic supply current test is presented, which is used to cover resistive opens considered as “hard detectable” type of physical defects. The investigation of the efficiency in unveiling open defects is based on the evaluation analysis carried out on a six transistor (6T) SRAM cell designed in a 90nm CMOS technology, where parasitic components of word lines, bit lines, and power supply lines are derived from a 4096-bit SRAM array. Three possible approaches to the dynamic supply current test are proposed and compared. Finally, achieved results are analyzed and discussed.

Asymmetric Underlap in Scaled Floating Body Cell Memories

The asymmetric underlap device for a floating body cell is proposed without any extra process or photomask during fabrication. The electric field in the gate-drain underlap region is quietly relaxed. It is found that memory operation would fail in bipolar-based floating body cells because band-to-band tunneling significantly alters the body potential. Measurements show the proposed structure could indeed suppress the undesirable band-to-band tunneling greatly so that the bistable state via the parasitic bipolar junction transistor is ensured in scaled floating body cells. The parasitic capacitances in both word line and bit line are also reduced.

An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.

A Novel Dual-Bit MRAM Cell

A new dual-bit magnetic random acess memory (MRAM) cell of astroid switching type is proposed. The dual-bit stack consists of two conventional MRAM cells connected in series. The two cells are identical except that their cell geometry, anisotropy, and pinned or reference layer orientations are orthogonal to each other. A write scheme is proposed by using the word line and bit line current polarities to write the dual-bit pattern simultaneously. This method doubles the write speed as well as minimizes the writing window margin reduction

Transmission Line Analysis of MRAM Cell

A test configuration of magnetic random access memory (MRAM) unit cell was modeled and its three-dimensional finite element method (FEM) analysis was utilized to calculate S-parameters. Transmission line analysis was performed for word line, bit line and readout signal path. Line width was varied from 0.5 to 2 /spl mu/m, line thickness from 0.1 to 1 /spl mu/m, and line length from 200 to 800 /spl mu/m. The sense signal path was modeled as a composite of transmission lines and RC lumped elements. As the thickness of insulator between the bit and sense lines increased from 50 to 150 nm, 3 dB attenuation frequency was increased by more than 1.7 times due to decreased capacitance between the lines.

Optimizing Write Current and Power Dissipation in MRAMs by Using an Astroid Curve

Analytical expressions of minimum electric current and power dissipation, and bit line and word line currents that produce them, for writing data into magnetic tunnel junction (MTJ) magnetoresistive random access memory (MRAM) cells are derived with the assumption that an asteroid curve can be applied to all MTJs in a memory cell array. The expressions contain word length, that is, the number of bits per word, and parasitic resistances of the write word line and bit line (which are important design parameters of memory cell arrays) and distances between the write currents and the free magnetic layer for data storage (which are important structural parameters of MTJ cells). They provide quantitative MRAM design guidelines and help to understand current and power behavior. For example: 1) the current along the bit lines should be decreased and the current along the write word line should be increased as the word length increases; 2) the word line currents for the minimum total current and power dissipation have maximum values at certain word line distances from the free layer; and 3) the minimum current and power have tendencies to saturate as the word length increases. Plots of the expressions exemplify the current and power dissipation behavior and dependence on the parameters related to the design of MRAM and MTJ cells.

The effect of variation of the WF 6 flow rate on the contact resistance in the DCS-based WSi x deposition

We analyze the Si/W composition ratio and distributions of phosphorus (P), fluorine (F) and chlorine (Cl) in tungsten silicide thin films as a function of WF 6 flow rate in a dichlorosilane-based deposition process. We investigate the effect of physical properties on the contact resistance between word line and bit line in the DRAM device. In RBS measurements, it is shown that Si/W composition ratio increases from 2.05 to 2.24 after annealing as WF 6 flow rate is decreased. This result was also confirmed by AES analysis. Also, in SIMS analysis, the concentration of phosphorus in the doped poly-Si consisting underlayer after WSi x deposition decreases from 4.75×10 20 to 5.1–5.3×10 19 atoms/cm 3 after annealing and the concentrations of phosphorus in the WSi x thin film increases with the decrease of WF 6 flow rate. But, the concentrations of chlorine does not change noticeably although the concentrations of fluorine tend to decrease as the WF 6 flow rate is decreased. The contact resistance of word line and bit line is found to considerably reduce from 13.6 to 3.0 μΩ-cm 2 as the WF 6 flow rate is decreased.

Whatever Happened to Information Theory in Psychology?

Although Shannon's information theory is alive and well in a number of fields, after an initial fad in psychology during the 1950s and 1960s it no longer is much of a factor, beyond the word bit, in psychological theory. The author discusses what seems to him (and others) to be the root causes of an actual incompatibility between information theory and the psychological phenomena to which it has been applied.

Plasma enhanced chemical vapor deposition Si-rich silicon oxynitride films for advanced self-aligned contact oxide etching in sub-0.25 μm ultralarge scale integration technology and beyond

We intentionally introduced excessive Si during the SiOxNy film deposition in order to increase the etch selectivity-to-SiOxNy for advanced self-aligned contact (SAC) etching in sub-0.25 μm ultralarge scale integration devices. The SiOxNy layer was deposited at a conventional plasma enhanced chemical vapor deposition chamber by using a mixture of SiH4, NH3, N2O, and He. The gas mixing ratio was optimized to get the best etch selectivity and low leakage current. The best result was obtained at 10% Si–SiOxNy. In order to employ SiOxNy film as an insulator as well as a SAC barrier, the leakage current of SiOxNy film was evaluated so that SiOxNy may have the low leakage current characteristics. The leakage current of 10% Si–SiOxNy film was 7×10−9 A/cm2. Besides, the Si-rich SiOxNy layer excellently played the roles of antireflection coating for word line and bit line photoresist patterning and sidewall spacer to build a metal–oxide–semiconductor transistor as well as a SAC oxide etch barrier. The contact oxide etching with the Si-rich SiOxNy film was done using C4F8/CH2F2/Ar in a dipole ring magnet plasma. As the C4F8 flow rate increases, the oxide etching selectivity-to-SiOxNy increases but etch stop tends to happen. Our optimized contact oxide etch process showed the high selectivity to SiOxNy larger than 25 and a wide process window (⩾5 sccm) for the C4F8 flow rate. When the Si-rich SiOxNy SAC process was applied to a gigabit dynamic random access memory of cell array, there was no electrical short failure between conductive layers.

Perspectives on giga-bit scaled DRAM technology generation

As the density of DRAM approaches giga-bit scaled DRAM, many critical challenges emerge from its small cell size. The most critical obstacles are insufficient cell capacitance and large leakage current at storage junction. Besides, variation of threshold voltage of memory cell transistor and the increased delay of word line and bit line come up to limit performance of device. In this paper, the critical issues in giga-bit technology are reviewed and appropriate approaches to overcome these issues are discussed based on the technology generation. The discussions are mainly focused on the key technologies: memory cell capacitor technology, memory cell transistor technology, word line and bit line technology, memory cell connection technology and metallization technology. Down to the 0.10 μm technology generation, we can specifically define the challenges for each technology generation and can find the ways to overcome these obstacles with proper technology migrations based on the current Capaciton-Over-bit line cell structure. The technology migration will move toward Ta 2O 5 capacitor, modified memory cell transistor, W-gate, W-bit line and self-aligned landing pad technology in cost-effective ways. Beyond the 0.10 μm technology generation, breakthrough technology seems to be indispensable. The breakthrough technology should happen in memory cell concept, memory cell structure and integration technology.

A 32×32-b adiabatic register file with supply clock generator

A 32/spl times/32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 /spl mu/m complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit.