Wireless Network-on-Chip Research Articles

Optimization Trends for Wireless Network On-Chip

Designing sustainable and high-performance wireless multi-core chips requires a matchless tradeoff between many aspects including scalable and reliable architectures implementation which in its turn implies aware-wideband energy-efficient wireless interfaces and adopting innovative straightforward optimization approaches to achieve the optimal configuration with a minimal cost. This paper focuses on investigating various existing designs and methodologies for wireless network on chip (WiNoC) architectures, as well as the different emerging technologies and optimization tools for the design of a robust and reliable WiNoC infrastructure with a special focus on combinatorial optimization meta-heuristics.

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs enable communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing in which hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in NoC-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

Scalable THz Network-On-Chip Architecture for Multichip Systems

While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture. In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips. Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication. The low-loss property of this waveguide lets us increase the number of chips. Each chip has a wireless node as a gateway for communicating with other chips. To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm. Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one. Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8 % , while for millimeter-wave NoC, this reduction is about 21 % . Furthermore, the average latency growth of our system is only 1 % compared with about 40 % increase for the millimeter-wave NoC.

Traffic-aware performance optimization in Real-time wireless network on chip

Network on Chip (NoC) is a prevailing communication platform for multi-core embedded systems. Wireless network on chip (WNoC) employs wired and wireless technologies simultaneously to improve the performance and power-efficiency of traditional NoCs. In this paper, we propose a deterministic and scalable arbitration mechanism for the medium access control in the wireless plane and present its analytical worst-case delay model in a certain use-case scenario that considers both Real-time (RT) and Non Real-time (NRT) flows with different packet sizes. Furthermore, we design an optimization model to jointly consider the worst-case and the average-case performance parameters of the system. The Optimization technique determines how NRT flows are allowed to use the wireless plane in a way that all RT flows meet their deadlines, and the average case delay of the WNoC is minimized. Results show that our proposed approach decreases the average latency of network flows up to 17.9%, and 11.5% in 5 × 5, and 6 × 6 mesh sizes, respectively.

A novel arbitration mechanism for crossbar switch in wireless network-on-chip

Wireless network-on-chip (WiNoC) has been introduced as an efficient communication paradigm that can provide high bandwidth and low latency wireless links among long-distance cores. However, the increase of demand for using these shared wireless links and the presence of few numbers of these channels on a chip leads to port contention in WiNoCs. This problem increases the average packet latency as well as the network latency. Therefore, a fair arbitration mechanism is required to eliminate port contention in wireless routers (WRs) and improve the utility of the output port. In this study, we propose a new arbitration mechanism for crossbar switch that can fairly allocate the port priorities based on the current traffic load and the wireless channel bandwidth. The simulation results under synthetic traffic patterns show that the proposed arbitration scheme reduces the average latency and improves the network throughput compared to round robin-based WiNoC.

Flow control and scheduling mechanism to improve network performance in wireless NoC

Today's, a promising solution, namely wireless network-on-chip (WiNoC) is utilized in multi-core systems to overcome the constraints of conventional on-chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi-hop communications. However, the buffer size of the WR antenna is limited, and under heavy traffic loads, it's filled and congestion occurs. On the other hand, network performance is degraded severely in the presence of head-of-line (HOL) blocking. Therefore, flow control and scheduling mechanisms are vital for improving the performance of WiNoCs. In this study, a flow control scheme based on an active queue management algorithm, and a priority-based scheduling strategy are suggested. The proposed mechanisms are evaluated under uniform and Bit-complement traffic patterns with different packet injection rate. The simulation results show that the proposed schemes have a significant impact on performance parameters, such as latency and throughput. Moreover, the saturation packet injection rate in WiNoC with four WRs is improved to about 33% under uniform traffic and is increased up to about 50% under the Bit-complement traffic pattern. This is increased by 16 and 50% in WiNoC with 16 WRs for uniform and Bit-complement traffic patterns, respectively, compared to the conventional WiNoCs.

Fault-tolerant design for data efficient retransmission in WiNoC

There is a sharp decline in the network performance when the wireless link fails as a data path in the Wireless Network-on-Chip (WiNoC). To counteract this problem, we propose a fault-tolerance mechanism for the efficient retransmission of data in the WiNoC. When an error is detected in the data transmission process, this mechanism works to feed back the fault information to the source node in real time via fault signal lines. In the source node, the highest transmission priority is assigned to the backup retransmitted data, and the corresponding direct link is positioned to enable the data packet for its efficient retransmission to the destination node, thereby ensuring efficiency in fault tolerance. Additionally, we have improved the receiving port of the wireless router, added the corresponding redundant buffers and mux, and dynamically selected the retransmitted non-faulty data packets to be written to the local router in order to avoid the disorderly retransmission of the data packets. The evaluation results of this paper demonstrate that compared with the methods which are under different fault conditions, this fault-tolerant method drastically improves the data throughput rate, reduces the delay, effectively guarantees the reliability of the network, and improves the system performance.

A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips

Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC architectures differ in the position of the wireless routers and how they interact with other routers. So, the placement of wireless interfaces is an important step in designing WiNoC architectures. In this paper, we propose a simulated annealing (SA) placement method which considers the routing algorithm as a factor in designing cost function. To evaluate the proposed method, the Noxim, which is a cycle-accurate network-on-chip simulator, is used. The simulation results show that the proposed method can reduce flit latency by up to 24.6% with about a 0.2% increase in power consumption.

A survey and taxonomy of congestion control mechanisms in wireless network on chip

Wireless network on chip (WiNoC) has been proposed as a promising solution for on-chip interconnection network due to high scalability, high bandwidth, and low latency. However, the variations of traffic pattern distribution and data flow lead to congestion in wireless interfaces-equipped routers (WRs). Congestion is one of the main challenges in emerging WiNoCs that can reduce network performance. In recent years, various researches have been proposed to decrease congestion in WiNoCs. However, this paper presents a comprehensive survey of the significant congestion control mechanisms in WiNoCs. The available schemes are classified into six categories, includeing hardware resources-based congestion control, congestion-aware routing algorithms, medium access control protocol,congestion-aware architectures, rate-based congestion control, and application-mapping with task-migration techniques. The goal of this survey is to highlight the characteristics and inherent constraints of congestion control mechanisms in a novel approach that can help researchers for designing efficient congestion control scheme.

Exploiting Data Resilience in Wireless Network-on-chip Architectures

The emerging wireless Network-on-Chip (WiNoC) architectures are a viable solution for addressing the scalability limitations of manycore architectures in which multi-hop long-range communications strongly impact both the performance and energy figures of the system. The energy consumption of wired links as well as that of radio communications account for a relevant fraction of the overall energy budget. In this article, we extend the approximate computing paradigm to the case of the on-chip communication system in manycore architectures. We present techniques, circuitries, and programming interfaces aimed at reducing the energy consumption of a WiNoC by exploiting the trade-off energy saving vs. application output degradation. The proposed platform—namely, xWiNoC—uses variable voltage swing links and tunable transmitting power wireless interfaces along with a programming interface that allows the programmer to specify those data structures that are error-resilient. Thus, communications induced by the access to such error-resilient data structures are carried out by using links and radio channels that are configured to work in a low energy mode, albeit by exposing a higher bit error rate. xWiNoC is assessed on a set of applications belonging to different domains in which the trade-off energy vs. performance vs. application result quality is discussed. We found that up to 50% of communication energy saving can be obtained with a negligible impact on the application output quality and 3% in application performance degradation.

TSV Antennas for Multi-Band Wireless Communication

On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. This work challenges the on-chip antenna design conventions, and pushes toward a Through-Silicon Via-based antenna design called TSV_A that establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30mm on-chip distance. The TSV_A performance is evaluated in both Finite Element Method and system-level Network-on-Chip (NoC) simulations. A comparison to traditional wire-based NoCs, analysis of wireless multi-bands, and technology scaling to demonstrate the substantial area improvements compared to traditional wireless NoCs (up to 99.88%) are performed. Simulation results show an improvement in network latency up to ~13% (average improvement of ~7%), energy-delay improvements of ~34% on average, and an improvement in throughput up to ~34% (average improvement of ~23%), using Wireless NoC with multi-band TSV_As. The improved signal performance of TSV_A, and multi-band capabilities, are ideal for wireless intercell communication for programmable metasurfaces with dedicated communication layers.

Attacks Toward Wireless Network-on-Chip and Countermeasures

A Wireless Network-on-Chip (WiNoC) offers a promising solution to reduce broadcast and long distance communication bottlenecks of conventional architectures by augmenting them with single hop wireless links. In this article, we discuss new security vulnerabilities and countermeasures to protect against them in a WiNoC based system. In particular, we describe Malicious Threshold Configuration (MTC) Attack, Disruptive Token Passing (DTP) Attack, Data Stealing by Broadcast (DSB) Attack and Hybrid Attack against the WiNoC. Our proposed countermeasure against MTC-OU (over-utilization) attack i.e., Source Destination checking mechanism decreases wireless hub utilization by 49% and network latency by many orders of magnitude compared to without countermeasure, causing system performance improvement. Another proposed countermeasure against DTP attacks i.e., detour mechanism improves the network throughout by 1.21x and 23x under DTP-AHT and DTP-DOS attacks respectively.

A design flow for an optimized congestion-aware application-specific wireless network-on-chip architecture

Wireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative communication infrastructure for the conventional wire-line NoC to achieve higher performance and low energy dissipation in on-chip communications. However, as realistic applications have different communication requirements, application-specific platforms are attractive to guarantee a specific level of performance. Moreover, the congestion probability over wireless routers is high, because each wireless router is shared by a group of cores. Therefore, we propose a novel methodology for designing an optimized congestion-aware application-specific WiNoC architecture. This methodology utilizes a novel mesh-of-tree (MoT) topology as a communication infrastructure to exploit the benefits of both mesh and tree topologies. Then, for a given application, the long-distance wire/wireless links are inserted into the MoT topology by considering the optimization of system cost and performance simultaneously. Furthermore, a congestion-aware layered routing is presented to reduce the congestion probability. Through cycle-accurate simulations, the performance of the proposed architecture has been evaluated and compared with state-of-the-art works under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption. Moreover, the area overhead associated with the proposed WiNoC architecture is investigated. The experimental results confirmed that the proposed MoT-based WiNoC architecture is a very competitive architecture among the alternative WiNoC architectures.

Cm3WiNoCs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-on-Chip

Millimeter-wave (mm-Wave) technology has been widely adopted in recent wireless network-on-chip (WiNoC) design since it is fully compatible with current CMOS process. By employing efficient channel multiplexing mechanisms, the performance of WiNoCs can be improved. However, such improvement is very limited since the wireless channels are generally shared by multiple pairs of communicating nodes and as the network size scales up, the multiplexing mechanisms perform worse. In this work, more physically achievable mm-Wave channels are introduced in WiNoCs, based on which, a high-performance millimeter-wave multichannel WiNoC architecture is elaborated which includes designs of topology, routing and MAC mechanism. Besides, to relieve the congestion in hubs, a congestion-aware adaptive channel selection (CAACS) mechanism is also proposed. Simulation results show that such an architecture increases the saturated throughput by 16%~98% and by introducing the CAACS mechanism, the saturated throughput can be further improved by up to 17%. The average packet delay is also significantly reduced while just negligible area and energy overhead are produced.

Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey From Millimeter-Wave to Terahertz and Optics

The miniaturization of transceivers and antennas is enabling the development of Wireless Networks-on-Chip (WNoC), in which chip-scale communication is utilized to increase the computing performance of multi-core/multi-chip architectures. Although the potential benefits of the WNoC paradigm have been studied in depth, its practicality remains unclear due to the lack of a proper characterization of the wireless channel at the chip scale and across the spectrum, among others. In this paper, the state of the art in wave propagation and channel modeling for chip-scale communication is surveyed. First, the peculiarities of WNoC, including the design drivers, architecture, environment, and on-chip electromagnetics are reviewed. After a brief description of the different methods to characterize wave propagation at chip-scales, a comprehensive discussion covering the different works at millimeter-wave (mmWave), Terahertz (THz) and optical frequencies is provided. Finally, the major challenges in the characterization of the WNoC channel and potential solutions to address them are discussed, providing a roadmap for the foundations of practical WNoCs.

Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation

Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.

Congestion-aware wireless network-on-chip for high-speed communication

The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC) architectures. The proposed system deals with the utilization of on-chip antennas for the wireless communication between the long distance cores to minimize the latency and power. In this proposed work, we have designed high-speed wireless NoC (WiNoC) for on-chip communication. This high-speed WiNoC has been achieved by designing a congestion measure unit, which monitors and measures the congestion in the input data and establishes the effective wireless communication between the output channels and routers. The designed architecture is synthesized and implemented by using Altera Quartus II, where the SoC is designed using Qsys builder. The proposed WiNoC shows better performance parameters like throughput, latency and power than the conventional NoC.

Design and Implementation of FPGA Based Configurable AI Architecture with Deep Learning Algorithm

Our main aim is to design a reconfigurable FPGA architecture using Network on chip using deep learning which act as a validation algorithm. In the Existing System we were using WiNoC (wireless network on chip)which was not reconfigurable. The energy saving in existing model was 55% whereas the proposed model saves upto 83 % of energy. Within the projected system Deep Learning formula is developed in VLSI design with acceptable model is intended on FPGA SOC chip, by that performance are analysed in terms of error rate, regression rate, confusion rate.

Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips

On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10 −10 . Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.

Channel Modeling and Characterization for Wireless Networks-on-Chip Communications in the Millimeter Wave and Terahertz Bands

Wireless networks-on-chip (WiNoC) communications are envisioned as a promising technology to support the interconnection of hundreds of cores in the chip multi-processor design. To meet the future demand for Tera-bit-per-second (Tbps) ultra-fast links in WiNoC, the millimeter wave (mmWave) and Terahertz (THz) bands with ultra-broad spectrum resource are attractive for WiNoC communications. In this paper, a hybrid WiNoC architecture and the CMOS-based stratified chip design are described, in which the flip-chip (FC) package and heat sink are considered. In the WiNoC stratified medium, electromagnetic fields are rigorously analyzed by using Sommerfeld integration, which is verified with full-wave simulation. Based on the developed channel model, the WiNoC propagation is thoroughly characterized by analyzing the path loss, the channel capacity, and reliability. Simulation results show that 0.95 Tbps wireless link with the error rate below 10−14 is achievable for WiNoC communications in the mmWave and THz bands. Furthermore, the impact and guidelines of the chip design on the WiNoC wave propagation are investigated. In particular, the wave propagation performance in the THz WiNoC channel can be improved by decreasing the underfill thickness, proper choice of the silicon thickness, and inserting a bottom layer below the silicon substrate.