A design flow for an optimized congestion-aware application-specific wireless network-on-chip architecture

Abstract

Wireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative communication infrastructure for the conventional wire-line NoC to achieve higher performance and low energy dissipation in on-chip communications. However, as realistic applications have different communication requirements, application-specific platforms are attractive to guarantee a specific level of performance. Moreover, the congestion probability over wireless routers is high, because each wireless router is shared by a group of cores. Therefore, we propose a novel methodology for designing an optimized congestion-aware application-specific WiNoC architecture. This methodology utilizes a novel mesh-of-tree (MoT) topology as a communication infrastructure to exploit the benefits of both mesh and tree topologies. Then, for a given application, the long-distance wire/wireless links are inserted into the MoT topology by considering the optimization of system cost and performance simultaneously. Furthermore, a congestion-aware layered routing is presented to reduce the congestion probability. Through cycle-accurate simulations, the performance of the proposed architecture has been evaluated and compared with state-of-the-art works under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption. Moreover, the area overhead associated with the proposed WiNoC architecture is investigated. The experimental results confirmed that the proposed MoT-based WiNoC architecture is a very competitive architecture among the alternative WiNoC architectures.