Enhancing interconnection network topology for chiplet-based systems: An automated design framework

Abstract

Chiplet-based systems integrate discrete chips on an interposer and use the interconnection network to enable communication between different components. The topology of the interconnection network poses a significant challenge to overall performance, as it can greatly affect both latency and throughput. However, the design of the interconnection network topology is not currently automated. They rely heavily on expert knowledge and fail to deliver optimal performance. To this end, we propose an automated design framework for chiplet interconnection network topology, called CINT-AD. To implement CINT-AD, we first investigate topology-related properties from the perspective of design constraints and structural symmetry. Then, using these properties, we develop an automated framework to generate the topology for interposer interconnections between different chiplets. A deadlock-free routing scheme is proposed for the topologies generated by CINT-AD to fully utilize the resources of the interconnection network. Experimental results show that CINT-AD achieves lower average latency and higher throughput compared to existing state-of-the-art topologies. Furthermore, power and area analysis show that the overhead of CINT-AD is negligible.