A Demand-Based Structure for the Architecture of Wireless Networks on Chip

Abstract

Wireless networks on chip (WiNoC) are considered to be a novel approach for designing efficient and scalable systems. The rationale behind this new approach is to reduce power consumption and latency in traditional network-on-chip architecture. Indeed, wireless links (WLs) in WiNoC architecture are shortcuts for the fast data transmission between distant cores. However, the presence of wireless equipment in WiNoC architecture leads to an increase in cost and area. In this paper, with respect to the facility location problem, the researchers attempted to optimally allocate wireless routers (WRs) to the processing elements. The methods of simulated annealing (SA), binary genetic algorithm (BGA) and binary particle swarm optimization (BPSO) were used for optimization under different traffic patterns. The results obtained from the simulations of this study indicate that BGA has higher efficiency than SA and BPSO. Furthermore, the resulting structure has fewer WRs, WLs and relatively desirable performance.