Wireless Network-on-Chip Research Articles

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors

With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects cause high latency and consume excess energy in NoC architectures. Emerging technologies such as on-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose A-WiNoC , a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores. To implement such adaptability in our network at run-time, we propose an adaptable algorithm that works in the background along with a token sharing scheme to fully utilize the wireless bandwidth efficiently. Since no wireless NoC design has been completely realized with current technology, we describe technology trends in designing energy-efficient wireless transceivers with emerging technologies. We compare our proposed A-WiNoC to both wireless and wired topologies at 64 cores, with results showing a 1.4-2.6 $\times$ speedup on real applications and a 54 percent improvement in throughput for synthetic traffic. Using Synopsys Design Compiler, our results indicate that A-WiNoC saves 25-35 percent energy over other state-of-the-art networks. We show that A-WiNoC can scale to 256 cores with an energy improvement of 21 percent and a saturation throughput increase of approximately 37 percent.

Hierarchical approach for hybrid wireless Network-on-chip in many-core era

Due to high latency and high power consumption in long hops between operational cores of Network-on-Chips (NoCs), the performance of such architectures has been limited. Billions of transistors available on a single chip present opportunities for new levels of computing capability. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless NoC has been emerged. Employing wireless communication links between cores, wireless NoC has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in wireless NoCs. Thus, in this paper, we introduce a hybrid wireless NoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are handled almost by single-hop wireless links. Simulation results show that HiWA efficiently reduces power consumption by 39% in comparison with a traditional wireless NoC, called WiNoC, while still achieves 16% lower packet latency than conventional NoC.

A CLOSED LOOP POWER MANAGER FOR TRANSMISSION POWER CONTROL IN WIRELESS NETWORK-ON-CHIP ARCHITECTURES

In wireless Network-on-Chip (WiNoC), radio frequency (RF) transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. Current WiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver radio hubs. This paper proposes a closed loop transmitting power control mechanism that, using bit error rate (BER) report obtained at receiver’s side, dynamically calibrates the transmitting power level needed for communication between the source and destination radio hubs to guarantee transmission reliability. Our proposed strategy achieves a significant total system energy reduction by about 40% with an average performance degradation of 3%.

A study of a wire–wireless hybrid NoC architecture with an energy-proportional multicast scheme for energy efficiency

The efficiency of interconnect network-on-chip (NoC) design significantly affects the thermal and energy-consumption problems. The wireless interconnect NoC (WiNoC) design provides a promising NoC architecture for multicast in chip multiprocessor (CMP) as compared with fully wired NoC. However, wireless routers (WRs) cost a larger area size as well as larger energy consumption than wired routers do. In this paper, we study a 2-tier wire–wireless hybrid NoC (WHNoC) architecture in an (NS)-processing-element (PE) CMP where N PEs use wires to connect with a wireless-enabled hub forming a star topology subnet and S wireless-enabled hubs form a fully connected WiNoC, named sWHNoC. We first investigate the performance of slotted p-persistent carrier sense multiple access (CSMA) protocol on the fully connected WiNoC. To greatly reduce the energy consumption of WiNoC, we propose an energy-proportional multicast scheme (EMS) by using a power-gating (PG) technique to switch off non-member WRs during the period of multicast transmission. A comprehensive comparison of the star-ring WHNoC, the mesh-based WHNoC, and the proposed sWHNoC is studied. Detailed analyses of the energy consumption of sWHNoC are presented. The correctness of analysis is validated by using Orion 2.0 simulator. Based on our investigation, the sWHNoC with the slotted p-persistent CSMA and the EMS will significantly reduce the energy consumption as well as the transmission latency in CMP.

Proposing an optimal structure for the architecture of wireless networks on chip

The need for more scalability in design on one hand and the occurrence of latency and high power consumption in communications between distant cores on the other hand are considered as the most common challenges which networks on chip encounter. Today, wireless network on chip (WiNoC) is regarded as a novel proposed approach in which wireless links are shortcuts for the fast data transmission between distant cores. However, the presence of Wireless routers (WRs) in WiNoC increases the cost and area. Thus, finding an optimal structure for communicating between cores is essential. In this paper, genetic algorithm (GA) and simulated annealing (SA) are compared with each other under different traffic patterns to find the best positions of WRs. The results obtained from the simulations of this study indicate that GA has higher efficiency than SA. Furthermore, the resulting structure has fewer WRs and relatively desirable performance.

On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of wireless network-on-chip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of: 1) the number of cores within the chip, and 2) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity), and network-level considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.

A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.

DVFS Pruning for Wireless NoC Architectures

The millimeter wave small world network on a chip is an emerging paradigm to design low power and high-bandwidth massive multicore chips. By reducing the hop count between largely separated communicating cores, wireless shortcuts in mSWNoC have been shown to carry a significant amount of the overall traffic within the network. The amount of traffic detoured in this way is substantial and the low power wireless links enable energy savings [1]. The overall energy dissipation and thermal profile of the mSWNoC can be improved even further if the characteristics of the wireline links and associated switches are optimized according to the traffic patterns. Dynamic voltage and frequency scaling (DVFS) is a popularmethodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance.We have already demonstrated that DVFS enables improvement of power and thermal profiles of mSWNoC-enabled multicore chips.

An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures

Modern systems-on-chip (SoCs) today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs) use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM) is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.

An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip

This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications. Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier. Novel dual gain-boosting techniques improve the gain, bandwidth, and out-of-band rejection of the ED. In addition, an actively-enhanced tunable inductor (AETI) load in the BB amplifier not only significantly reduces its area overhead, but also provides a tunable peaking level. Fabricated in a 65-nm bulk CMOS process, the OOK demodulator consumes only 4.6 mW from a 1-V supply, and occupies an active area of 0.043 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A maximum data rate of 18.7 Gb/s with a bit-error rate less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> is demonstrated through measurements, which translates to a bit-energy efficiency of 0.25 pJ/bit.

Formula omitted]-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs

Modern embedded SoC design uses a rapidly increasing number of processing units for ubiquitous computing, forming the so-called embedded many-core SoCs (McSoC). Such McSoC devices allow superior performance gains while side-stepping the power and heat dissipation limitations of clock frequency scaling. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. To bridge the widening gap between computation requirements and communication efficiency faced by gigascale McSoCs in the upcoming billion-transistor era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WiNoC), has been proposed by using the recently developed RF interconnect technology. With the high data-rate, low power and ultra-short range interconnection provided by UWB technology, the WiNoC design paradigm calls for effective solutions to overhaul the on-chip communication infrastructure of gigascale McSoCs.In this work, an irregular and reconfigurable WiNoC platform is proposed to tackle ever increasing complexity, density and heterogeneity challenges. A flexible RF infrastructure is established where RF nodes are properly distributed and IP cores are clustered. Consequently, a performance-cost effective topology is formed. A region-aided routing scheme is further deigned and implemented to realize loop-free, minimum path cost and high scalability for irregular WiNoC infrastructure. To implement the data transmission protocol, the RF microarchitecture of WiNoC is developed where the RF nodes are designed to fulfill the functions of distributed table routing, multi-channel arbitration, virtual output queuing, and distributed flow control. Our simulation studies based on synthetic traffics demonstrate the network efficiency and scalability of WiNoC.

Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-on-Chip

Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible millimeter-wave (mm-wave) transceivers can achieve significant improvements in energy-efficiency in on-chip data transfer for multicore chips. A token based medium access mechanism is used in mm-wave WiNoC architectures to enable a distributed utilization of the available wireless bandwidth among multiple transmitters. However, on-chip wireless interconnects can suffer from high rates of failures due to challenges in design and manufacturing. Consequently, the token-passing mechanism can fail and significantly degrade the potential benefits of this novel interconnect technology. In this paper, we establish a cross-layer robust and failure-resistant design methodology for WiNoC architectures. By optimizing the WiNoC topology and complementing it with a robust token management scheme and error correction codes, we propose to design a failure-resistent WiNoC. Through system-level simulations, we demonstrate that the proposed design can mitigate the effect of various types of failures of the wireless fabric in WiNoC architectures without compromising the energy-efficiency.

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

In view of the high energy consumption and latency problem due to multi-hop wired links between distant cores of traditional large-scale Network-on-Chip, a virtual torus-based adaptive wireless NoC architecture has been proposed when analyzing the existing several wireless NoC architectures. By not only adopting the automatic detection and dynamic bandwidth allocation mechanism to hot wireless link based on the sensing parameter for improved congestion measurement, but also designing the Dynamic Allocation Control Circuit Module (DACCM) for transmitter, the intra-chip topology and link bandwidth could be adaptively adjusted as different traffic patterns. Experimental results show that the proposed architecture has more significant latency improvement and energy saving under different traffic patterns or real application such benchmark as FFT.

Application Aware Topology Generation for Surface Wave Networks-on-Chip

The networks-on-chip (NoC) communication has an increasingly larger impact on the system power consumption and performance. Emerging technologies, like surface wave, are believed to have lower transmission latency and power consumption over the conventional wireless NoC. Therefore, this paper studies how to optimize the network performance and power consumption by giving the packet-switching fabric and traffic pattern of each application. Compared with the conventional method of wire-linked, which adds wireless transceivers by using the genetic algorithm (GA), the proposed maximal declining sorting algorithm (MDSA) can effectively reduce time consumption by as much as 20.4% to 35.6%. We also evaluate the power consumption and configuration time to prove the effective of the proposed algorithm.

Architecture and Design of Multichannel Millimeter-Wave Wireless NoC

The network-on-chip (NoC) is an enabling methodology to integrate many embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchanges. To address these problems, this paper introduces design methodology for a wireless NoC with multiple nonoverlapping channels. The authors present both the physical layer design and the overall interconnection architecture.

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

The mm-wave small-world wireless NoC (mSWNoC) has emerged as an enabling interconnection infrastructure for designing high-bandwidth and energy-efficient multicore chips. In this mSWNoC architecture, long-range communication predominately takes place through the wireless shortcuts operating in the range of 10--100GHz, whereas short-range data exchange occurs through conventional metal wires. This results in performance advantages (lower latency and energy dissipation), mainly stemming from using the wireless links as long-range shortcuts between far-apart cores. The performance gain introduced by the wireless channels can be enhanced further if the wireline links of the mSWNoC are optimized according to the traffic patterns arising out of the application workloads. While there is significant energy savings, and hence temperature reduction, in the network due to the mSWNoC architecture, a load-imbalanced network is still susceptible to local temperature hotspots. In this work, we demonstrate that by incorporating congestion-avoidance routing with network-level dynamic voltage and frequency scaling (DVFS) in an mSWNoC, the power and thermal profiles can be improved without a significant impact on the overall network performance. In this work, we demonstrate how novel interconnect architectures enabled by the on-chip wireless links coupled with power management strategies can improve the energy and thermal characteristics of an mSWNoC significantly without introducing any performance degradation with respect to the conventional mesh-based NoC.

Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction

Maximum likelihood (ML) phylogeny is an important statistical approach in computational biology that estimates the most likely evolutionary relationship among a given set of species. This paper demonstrates how wireless network-on-chip (WiNoC)-based multicore platforms can be employed to achieve faster time-to-solution ML phylogeny reconstruction.

Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures

Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multicore chips. WiNoCs based on small-world network architecture and designed with incorporating millimeter (mm)-wave on-chip wireless links offer significantly lower power and higher bandwidth compared to traditional mesh-based counterparts. In this mm-wave small-world WiNoC (mSWNoC), long distance communication predominately takes place through the wireless shortcuts whereas the short-range data exchange still occurs through the conventional metal wires. This results in performance advantages mainly stemming from using the wireless links as long-range shortcuts between far apart cores. This performance gain can be enhanced further if the wireline links and the processing cores of the WiNoC are optimized according to the traffic patterns and application workloads. In this work, we demonstrate that by incorporating both processor- and network-level dynamic voltage and frequency scaling (DVFS) in an mSWNoC, the power and thermal profiles can be improved without a significant impact on the overall execution time. We also show that depending on the applications, temperature hotspots can be formed either in the processing cores or in the network infrastructure. The proposed dual-level DVFS is capable of addressing both types of hotspots. In this work we will demonstrate how novel interconnect architectures enabled by the on-chip wireless links coupled with power management strategies can improve the energy and thermal characteristics of a NoC significantly.

CDMA Enabled Wireless Network-on-Chip

Multihop communication links in conventional Networks-on-Chips (NoCs) results in lower rates of data transfer and higher energy dissipation. Long-range millimeter-wave wireless interconnects were envisioned to alleviate this problem. However, the available bandwidth of the wireless channels is limited and hence an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. In this article we show that with multiple simultaneous access of the shared wireless medium using a Code Division Multiple Access (CDMA) scheme the peak performance can be improved significantly while lowering energy dissipation in data transfer compared to the conventional wireline counterparts as well as state-of-the-art Wireless NoCs using similar technologies. We present a thorough analysis of the reliability in data transfer using the CDMA based wireless links and show that a reliability-aware architecture design with CDMA based wireless links can lower the energy dissipation in NoC fabrics without compromising the achievable robustness.

3D NoC with Inductive-Coupling Links for Building-Block SiPs

A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips.