Wireless Network-on-Chip Research Articles

Retraction Note: Tree-based wireless NoC architecture: enhancing scalability and latency

Retraction Note: Tree-based wireless NoC architecture: enhancing scalability and latency

Performance and energy evaluation of dynamic adaptive deterministic routing algorithm for multicore architectures

Chip Multiprocessors (CMPs) leverage multiple processing units to improve computational speed and efficiency. Routing algorithms in NoC (Network-on-Chip) architectures ensure efficient data communication between these units, addressing challenges such as congestion, latency, and power consumption. This paper delves into an extensive analysis of the performance evaluation concerning the Dynamic Adaptive Deterministic (DyAD) routing for Network-on-Chip (NoC) and Wireless Network-on-Chip (WiNoC) configurations within the framework of a 64-core and 100-core multicore architecture. The evaluation involved a congestion threshold analysis of data transmission latency, the efficiency of network data throughput, and the amount of energy consumed. To substantiate our conclusions, we conducted simulations of the 64-core and 100-core mesh-based NoC and WiNoC architectures under the Video Image Processing System (VIPS) benchmark workload. These simulations were executed utilizing the Noxim simulator, a well-recognized tool acclaimed for its capacity to provide cycle-accurate simulations. Analyzing the simulation outcomes, it becomes evident that the DyAD routing approach for the 64-core and 100-core WiNoC architecture performs better in terms of network performance. It is characterized by enhanced capabilities at higher Packet Injection Rate (PIR) saturation loads, improved network throughput, and minimized latencies. This dominance is evident from its ability to handle heavier workloads and achieve lower delays in the investigated VIPS workload situations, compared to the 64-core and 100-core NoC multicore architecture.

Exploring distance-based wireless transceiver placements for wireless network-on-chip architecture with deterministic routing algorithms

Network-on-chip (NoC) technology is crucial for integrating multiple embed-ded computing cores onto a single chip. Consequently, this has led to the de-velopment of the wireless network-on-chip (WiNoC) concept, seen as a promis-ing strategy to overcome scalability issues in communication systems withinchips for future many-core architectures. This research analyses the impactof wireless transceiver subnet clustering on the hundred-core mesh-structuredWiNoC architecture. The study aims to examine the effects of distance-basedwireless transceiver placements on the transmission delay, network throughput,and energy consumption within a mesh wireless NoC architecture featuring ahundred cores, under specific routing strategies: X-Y, west-first, negative-first,and north-last. This research investigates the impact of positioning radio sub-nets at the farthest, farther, nearest, and closest positions within an architectureequipped with four wireless transceivers. The Noxim simulator was utilised tosimulate the analysed wireless transceiver placements within the hundred-coremesh-structured WiNoC designs, with the objective of validating the results.The architecture with the wireless transceivers positioned at midway proxim-ity (nearer and further) demonstrated the best performance, as evidenced by thelowest latencies for all evaluated deterministic routing algorithms, according tothe simulation outcomes.

Energy-aware application mapping methods for mesh-based hybrid wireless network-on-chips

The 2D mesh topology-based Network-on-Chip (NoC) is a prevalent structure in System-on-Chip (SoC) designs, offering implementation and fabrication benefits. However, increased NoC scale leads to longer communication paths, more hops, and higher end-to-end latency and energy consumption. To mitigate these issues, Wireless NoC (WiNoC) integrates wireless communication, enhancing data rates, energy efficiency, and routing flexibility. Despite several mapping algorithms for NoCs, optimal techniques for hybrid WiNoCs are underexplored. This study proposes two novel application mapping methods for 2D mesh topology-based hybrid WiNoCs, using quadratic programming (QP) and simulated annealing (SA). Our goal is to minimize communication-related energy consumption. We evaluated these methods across various wireless router configurations, benchmarks, and custom application graphs. The QP-based method excels in smaller problems, while the SA-based approach yields optimal or near-optimal results for larger sizes within practical runtimes.

RETRACTED ARTICLE: Tree-based wireless NoC architecture: enhancing scalability and latency

RETRACTED ARTICLE: Tree-based wireless NoC architecture: enhancing scalability and latency

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs

Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due to the varying traffic density across the WNoC. Moreover, the conventional WNoCs give equal importance to all the traffic taking the wireless path and transmit it in an oldest-first manner. Nevertheless, the critical data can degrade the system performance to a large extent by delaying the application runtime if not served promptly. We propose 2DMAC, which can change the token arbitration pattern and tune the channel hold time of each WI based on its runtime traffic density and criticality status. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer. The proposed mechanism improves the wireless channel utilization by 15.67% and the network throughput by 29.83% and reduces the critical data latency by 29.77% over the traditional MAC.

Proactive flow control using adaptive beam forming for smart intra-layer data communication in wireless network on chip

Systems-on-chips need numerous predesigned cores to advance. NoC enables Multi-Core SoCs (MC_SoCs). Conventional NoC cores use power and latency on multi-hop wired connections. An effective Wireless Network-on-Chip (WiNoC) architecture can overcome NoC difficulties. On-chip antennas, transceivers, and routers replace multi-hop cable connections with high-bandwidth single-hop wireless networks using WiNoC. Nanotechnology development demands fast data transfer to overcome performance bottlenecks from sharing memory modules and connecting fabrics. This research offers a new Proactive Flow control using Adaptive Beam formation for Smart Intra-layer Data Communication technique(PF_SDC) to optimally use network resources and assure QoS in Wireless Network-on-Chip for next-generation nano-domain technology. Hybrid NoC architecture optimises application admission for data transfer over wired and wireless interconnects. Data traffic is managed by a fuzzy inference-based Intelligent Head Agent (IHA). Queue load predicts router status for the fittest path selection. IHA initiates beams at angles to admit data flow towards the target while utilising the least amount of network power and resources. A simulation model shows that the proposed system may be applied in real-world applications and consumes little power with good throughput.

Workload-Aware WiNoC Design with Intelligent Reconfigurable Wireless Interface

By introducing wireless interfaces in conventional wired routers or hubs, wireless network-on-chip (WiNoC) is proposed to relieve congestion pressure from high volume inter-subnet data transmission. Generally, processing elements on chip receive input data and return feedback through network interface, and data transmission function in Network-on-Chip (NoC) is completed by routers. Hubs equipped with wireless interface are fixed to certain wired routers. While wireless channels may not be fully utilized due to unbalanced workload and constant hub-router connection, e.g., certain nodes processing excess inter-subnet data traffic are far away from hubs. In this paper, we proposed a workload-aware WiNoC design with intelligent reconfigurable wireless interface to improve wireless resources utilization and mitigate congestion. Through multidimensional analysis of traffic flow, a 4-layer neural network is trained offline and applied to analyze workload in each tile, and return three most potential tiles for wireless interface reconfiguration to fully utilize wireless channel and lowing latency. We also implement a historical traffic information-based reconfigurable scheme for comparation. Evaluation results show that in an 8 × 8 hybrid mesh topology, the proposed scheme can achieve 10%–16% reduction in network latency and 5%–11% increment in network throughput compared with fixed-link hub-node connection scheme under several mixed traffic patterns.

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

Optical Wireless Networks on-Chip are an emerging technology recently proposed to improve the interconnection between different processing units in densely integrated computing architectures. In this work, we propose a 4 × 4 optical wireless switch (OWS) based on optical phased arrays (OPAs) for broadband reconfigurable on-chip communication. The OPA and OWS design criteria are reported. Moreover, the performances of the OWS are analyzed and optimized considering the electromagnetic propagation in on-chip multilayer structures, with different thicknesses of the cladding layer. The effect on the OWS behavior of a non-ideal distribution of the power in input to the OPA is also investigated by designing a 1 × 7 beam splitter, based on a single-stage multi-mode interference (MMI) device to be used as a single element of the OWS. Then, the MMI output signals are considered in input to the transmitting OPAs and the OWS performances are evaluated.

Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC

Wireless network-on-chip (WiNoC) face serious reliability challenges, and the fault-tolerant design of wireless routers (WRs) has a significant impact on the transmission efficiency of the overall on-chip network. Due to the continuous shrinking of CMOS technology and the integration of wireless technology in complex circuits, WRs appear to become more prevalent. In this paper, we propose a dynamic detection strategy for wireless interface faults in WiNoC, which classifies the fault scenarios of wireless interfaces in WRs, implements wireless interface fault detection in WiNoC operation, and updates the fault scenarios. Meanwhile, a fault-free WR table-based nearest route algorithm is also presented to maximize the network performance. The Evaluations show that the proposed scheme can effectively guarantee the network performance when WR faults occur in the network and is also effective under the case of moderate WR fault rate.

Mathematical Modeling of Flow Control Mechanism in Wireless Network-on-Chip

Network-on-chip (NoC) is an effective interconnection solution of multicore chips. In recent years, wireless interfaces (WIs) are used in NoCs to reduce the delay and power consumption between long-distance cores. This new communication structure is called wireless network-on-chip (WiNoC). Compared to the wired links, demand to use the shared wireless links leads to congestion in WiNoCs. This problem increases the average packet latency as well as the network latency. However, using an efficient control mechanism will have a great impact on the efficiency and performance of the WiNoCs. In this paper, a mathematical modeling-based flow control mechanism in WiNoCs has been investigated. At first, the flow control problem has been modeled as a utility-based optimization problem with the wireless bandwidth capacity constraints and flow rate of processing cores. Next, the initial problem has been transformed into a dual problem without limitations and the best solution of the dual problem is obtained by the gradient projection method. Finally, an iterative algorithm is proposed in a WiNoC to control the flow rate of each core. The simulation results of synthetic traffic patterns show that the proposed algorithm can control and regulate the flow rate of each core with an acceptable convergence. Hence, the network throughput will be significantly improved.

Game-based congestion-aware routing algorithm in wireless network on chips

Wireless network on chip (WiNoC) has been introduced to alleviate some challenges with conventional NoC such as high latency and power consumption. Routing the packet through the wireless links for arriving to far apart destination leads to a shorter path. Therefore, many of nodes prefer to send their packets to nearest wireless router on the WiNoC. When the demand for a wireless node increases, the likelihood of the congestion increases. To address this problem, we propose a game-based yet simple routing algorithm to balance the traffic in this paper. The WiNoC is modelled with a mixed-strategy Bayesian-game in which the nodes are the players with two valid actions namely, routing the packets with and without the wireless links. The simulation results show that using the proposed mixed-strategy for considerably improves the performance of the network, more precisely, the system performance is improved 10%-42% compared with the previous related works.

Design of a Novel Wireless NoC Architecture for Chip Multiprocessor

The Network on chip is a new communication method of System on Chip. It is the main part of multi-core technology. A large number of embedded cores can be combined on a single chip. Due to the multi-hop characteristics of communication, there are some problems in the design of traditional NoC, such as high latency and power consumption. Thus, to handle the communication problem of long-distance transmission of traditional NoC, wireless Networks on Chip (WiNoC) has been proposed. Using WiNoC to design the multi-core System on Chip can significantly reduce the latency and energy consumption of the network. The advantage of using wireless network on chip is to replace the multi-hop path of traditional network on chip with wireless single hop link. However, due to the limited space on the chip and the cost, it is very important to determine the optimal number and correct location of wireless hubs. In this paper, we propose a new method to obtain the optimum configuration of a WiNoC by using the Co-evolutionary Algorithms (CA) and a wireless NoC architecture based on mesh. This work examines the effect of VC and sub-net size on WiNoC performance efficiency and energy under different packet injection rate (PIR) and the number of cores (64, 144 and 256). The simulation experiment of the algorithm proposed in the whole architecture has been implemented on the Noxim platform.

Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systems

Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systems

Novel Bi-UWB on-Chip Antenna for Wireless NoC

Communication between on-chip cores is a challenging issue for high-performance network-on-chip (NoC) design. Wireless NoC (WiNoC) represents an alternative design for planar wired interconnects, aiming to reduce latency and improve bandwidth. In this paper, a novel on-chip fractal antenna is designed and characterized. In order to disseminate interference affecting NoC performance in order to enhance on-chip quality of service (QoS), a set of exclusive sub-channels are assigned to each antenna. The proposed antenna has two wide bands (bi-WB)— and , of (63–78) GHz and (101–157) GHz, respectively. The multi-band antenna allows different channel allocations for on-chip core communications. This WiNoC design exhibits improved performance, due to its enhanced antenna bandwidth and the benefit provided by the developed algorithm that can scan and compare to assign the best (upload or download) sub-channels to each antenna.

Design of fully adaptive routing and hybrid VC allocation in wireless NOC

Wireless network-on-chip (WiNoC) establishes a long-range single-hop wireless links on the base of the traditional planar metal interconnects network, which improve network performance in several aspects. The establishment of wireless link improves the diversity of path for packet transmitting, while simultaneously aggravates the deadlock problem, leading it to more complicated condemn. The traditional routing mechanism of wireless network on chip can avoid deadlock by sacrificing the adaptability of transmitting, which leads to unbalanced and insufficient use of limited on chip resources. In this paper, a fully adaptive routing mechanism is proposed to balance buffer utilization. At the same time, we proposed a hybrid virtual channel allocation strategy in order to make full use of buffer resources. For a large number of single-flit wired packets and wireless packets, more aggressive non-atomic allocation is adopted, and the remaining packets are arranged with atomic allocation to avoid potential deadlock. Experimental results showed that compared with the traditional deadlock solutions, the proposed scheme introduces less area and power consumption, and balances the utilization of buffer resources. Under the non-uniform Traffic Patterns, the proposed scheme has better performance in terms of delay and throughput, achieves 62.0% improvement compared to the traditional counterpart.

Design of a Novel Wireless Noc Architecture for Chip Multiprocessor

Design of a Novel Wireless Noc Architecture for Chip Multiprocessor

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip

The communication performance over conventional long-distant routers cannot satisfy the requirements of future multi-core systems. Wireless Network-on-Chip (WiNoC) architecture with CMOS compatible transceivers is utilized to obtain significant improvement in on-chip data transfer for multi-core systems. The wireless routers (WRs) in WiNoC architecture provide wireless shortcuts to alleviate the latency of multi-hop communications. Despite the additional bandwidth of wireless shortcuts, the WRs are prone to congestion due to the limited number of wireless channels and the shared use of these channels under unbalanced load. On the other hand, network performance will be severely degraded when the presence of head-of-line (HOL) blocking. In this paper, we establish a congestion pre-avoidance and load-balanced wireless network-on-chip architecture. To implement such architecture in our network, firstly, we propose an dynamic XY-YX routing algorithm detour WR to pre-avoid the additional traffic flow of the wireless router; Secondly, the virtual output queue scheme is adopted to handle HOL blocking, and on this basis we design a wireless router micro-architecture; Finally, a threshold-based load-balanced mechanism is designed, which uses the number of buffered flit as a guideline to avoid unbalance load. Through system-level simulations, the results demonstrate that the proposed WiNoC architecture can mitigate negative effect of congestion in WR. And with appropriate hardware overhead, network transmission latency and network throughput are significantly improved.

Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip

Wireless Network-on-Chip (WiNoC) are being examined for parallel applications to improve the performances by reducing multi-hop latency. Wireless nodes handle massive data transmission assignment, the data bandwidth and energy efficiency of the WiNoC architecture can be improved by establishing wireless links to respond to dynamically changing traffic patterns. Among them, the wireless token mechanism is widely used, since it would take little additional hardware overhead and simple operation process. However, the traditional wireless token mechanism is a time-division-multiplexed fair strategy, and cannot well cope with non-uniform traffic patterns. In this paper, a priority-based dynamic media access control (MAC) mechanism in wireless network-on-chip is architected by redefining MAC mechanism, which aims to make wireless MAC protocols more suitable for non-uniform traffic patterns. Experimental results show that the proposed scheme in this paper guarantees the network performance equivalent to the traditional token mechanism in random traffic mode, and the network throughput is increased by 14%–15% in the hotspot mode. Compared with the traditional token mechanism, the average packet delay is greatly reduced before the saturation point with little extra hardware overhead introduced simultaneously.