Wire Sweep Research Articles

Experimental and Numerical Studies on the Deformation of a Flexible Wire in an Injection Moulding Process

The application of thermoplastic materials is state of the art due to their fast cycle times in production and large freedom of shaping. To enhance the performance and functionality, additional materials or elements are embedded into the bulk material. While typically fibres are added for mechanical reinforcement, recent research also focusses on the integration of conductor wires to integrate electrical functions. During the manufacturing process, the interaction with the thermoplastic melt can lead to breakage or undesired deformation of the flexible elements respectively wires. For a proper process and component design, this local fluid-structure-interaction must be understood and considered. There are different numerical approaches to meet this challenge. In the present work, the suitability of established modelling techniques and solvers is evaluated and compared with experimental investigations. For this purpose, solid flexible wires are overmoulded with polypropylene using an injection moulding testing set-up. In the experimental investigations, the deflection of the wire is evaluated for different process settings. For the numerical simulations, solvers from ABAQUS and Moldflow including the Wire Sweep Module and the Core Shift Module are used. The comparison of the simulations and the experiments shows, that the different solver’s results clearly deviate from each other and the experiment depending on the wire length. While some approaches seem to be very promising, it can be concluded that the longer the wire, the worse the simulation quality.

Process Optimization and Implementation of Online Monitoring Process in the Transfer Molding for Electronic Packaging

Abstract The quality of molded packages heavily depends on the process parameters of the molding process and on the material characteristics of epoxy molding compounds (EMCs). When defects are introduced into the electronic packages in one of the last steps in the manufacturing process, namely, during encapsulation, it may cause high failure costs. To decrease the number of defects due to the molding process, a comprehensive understanding of the impact of process parameters and variations in the characteristics of the EMC on package quality is necessary. This study aimed at supporting a deeper understanding of the influence of process parameters and variations in the material characteristics of the EMC on package quality. A systematic approach was introduced to generate a process model describing the correlation between process parameters and package quality to obtain optimum process parameters for the transfer molding process. The influence of the alterations in material characteristics of the EMC due to prolonged storage duration and humidity on void formation and wire sweep was investigated. An online monitoring method, dielectric analysis (DEA), was implemented into the transfer molding process to monitor the variations in the cure behavior of the EMC. A second molding compound was used to analyze the similarities in the alteration behavior of the molding compounds when subjected to the same preconditioning and to generalize the characteristic information obtained from DEA.

Life prediction of copper wire bonds in commercial devices using principal component analysis (PCA)

Copper has been widely adopted as a viable alternative to gold for wire bonding, due to its lower cost, better electrical and thermal conductivity, lower tendency for wire sweep due to a higher modulus and slower intermetallic compound (IMC) formation with aluminum bond-pad. However, these IMCs can cause an increase in resistance and separation between bonding interface which causes an open circuit. Wire bond and component reliability must consider all factors in combination with the change of wire bond materials and processes. How can users of off-the-shelf components determine the effects of wire bond material changes on the reliability of the components in their systems? How will these changes affect high reliability applications such as automotive, military and harsh environments?Although physics-of-failure based models can represent the failure mechanisms individually, the complex nature of the mixed failure mechanism has inhibited development of an analytical equation to represent it. In addition, geometrical and material characteristics of the entire package along with bonding process parameters play a crucial role in magnitude of stress experienced by these bonds, portraying difficulty in developing one such equation for use to all copper wire bonded devices. This study has aimed to develop a data-based predictive method based on the principal component analysis technique to provide an estimate of the wire bond time to failure for plastic encapsulate components. Extensive thermal cycling experiments have been performed on multiple commercial devices to obtain training data for the model. This method of wire bond fatigue and failure prediction is an adaptive technique which can achieve greater accuracy as more data is added. This method aims to provide a life-time estimate of copper wire bonded component with inputs such as initial geometrical, material properties, and wire bond related attributes for a specific package.

Wire Bonding Looping Solutions for High Density System-in-Package (SiP)

Abstract System-in-Package (SiP) have seen a lot of growth in recent years especially in mobile devices due to its higher level of system integration, more design flexibility and smaller form factor. Two or more semiconductor die and passive components are usually present in a SiP device. Die to die bonding and increased I/O density are two common challenges associated with wire bonding in SiPs. High density SiP packages often have high I/O counts and tight wire clearance. As a result, the requirements for wire bond looping are high. To avoid wire shorts, the wire bond loops need to be well designed in order to have optimal wire clearance between various tiers of wire loops as well as neighboring loops. The formed loops need to have low wire sway after wire bonding and low wire sweep after molding. Due to the existence of multiple dies and other passive components within the same package, special wire bond loops with long flat lengths and sharp bending angles are sometimes necessary to clear the die edges and the other components. In this paper, we will review a few new wire bonding looping solutions including 3D looping design software, 3D loop clearance checking and multi-tier loop formation improvements. A robust package design is essential to improve production yield. A 3D looping design software has been developed to evaluate the robustness of various package designs from a wire looping perspective. The software is able to detect potential issues early on in the design cycle and evaluate alternatives quickly, therefore reduces the time to market and improves design robustness. A spatial 3D clearance checking tool has been developed to detect any interference between the densely populated wire loops. The tool can also detect interference between the wires and the edges of different dies. Furthermore, the wire clearance against various components in the package can also be assessed. Process engineers can leverage the clearance check tool and the 3D visualization of wires, multiple dies and components to aid wire bonding looping optimization. Multi-tier looping requires a large range of loop height and wire length capability. In order to achieve optimal looping for high density multi-tier applications, a separate wire bonding looping software has been developed to generate optimal wire bonding motion trajectories that can achieve the loop shapes designed by the 3D looping design software. An example of 6 loop tier application is developed and results are analyzed to show the wire bonding capabilities including looping height from 75um to 500um and wire length up to 5mm.

A theoretical study to improve wire sag of ultra-long wire bond loops for 3D/MCM packaging

An innovative theoretical model by altering cross section of gold wire is proposed to reinforce the wire sag stiffness of a wire bond that suffered low yield for the applications of 3-dimensional and multi-chip module (MCM) packaging. The flexural rigidity of a wire bond is found to be a function of the material properties in the moment of inertia of a bond wire. Suffice to say, if the moment of inertia of the bond wire can be raised, the associated sag deflection will be diminished. By manipulating the moment of inertia of the bond wire, the sag deflection of the wire bond can be regulated appropriately to avoid wire sag and even the wire sweep enigma. The ellipse-like cross section of a wire bond is applied as a numerical example to improve the wire sweep stiffness or wire sag stiffness in this study. The results show the sag deflection of a wire bond can be reduced significantly if the ellipse-like cross section is oriented in the preferred direction of flexural rigidity of a wire bond. Furthermore, a systematic study of matching design is performed to control wire sag and wire sweep for the wire bonding applications of overhang cross-stacked and step-stacked packaging. It shows that to use a single diameter of bonding wire in these complicate bonding environments of overhang stacked configurations is a favored possibility. The advantages shown from the theoretical study need to be implemented in further work in a production environment on current wire bonding equipment.

The Effect of Epoxy Molding Compound Floor Life to Reliability Performance and mold ability for QFN Package

This research studied about an epoxy molding compound (EMC) floor life to reliability performance of integrated circuit (IC) package. Molding is the process for protecting the die of IC package form mechanical and chemical reaction from external environment by shaping EMC. From normal manufacturing process, the EMC is stored in the frozen at 5oC and left at around room temperature for aging time or floor life before molding process. The EMC floor life effect to its properties and reliability performance of IC package. Therefore, this work interested in varied the floor life of EMC before molding process to analyze properties of EMC such as spiral flow length, gelation time, and viscosity. In experiment, the floor life of EMC was varied to check the effect of its property to reliability performance. The EMC floor life were varied from 0 hours to 60 hours with a step of 12 hours and observed wire sweep, incomplete EMC, and delamination inside the packages for 3x3, 5x5 and 8x8 mm2 of QFN packages. The evaluation showed about clearly effect of EMC floor life to IC packaging reliability. EMC floor life is not any concern for EMC property, moldabilty, and reliability from 0 hours to 48 hours for molding process of 3x3,5x5 and 8x8 mm2 QFN packaging manufacturing

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

Effects of Stacked Layers and Stacked Configurations on Wire Sweep and Wire Sag of Advanced Overhang/Pyramid Stacked Packages

Overhang and/or pyramid stacked packages are the trend in the semiconductor industry. As the stacked layers increase drastically, the wire sweep and wire sag problems become more and more serious. Based on some types of frequently used stacked configurations, their corresponding wire sweep and wire sag stiffness and deflections are investigated for extra-high stacked layers. Two typical profiles of Q_loop and S_loop wire bonds are included in this study. However, wire sweep and wire sag have to be considered in two different design aspects. For wire sweep, we have the conclusion that the maximum wire sweep deflections always occur near the central segment of a wire bond. As for the wire sag, the maximum wire sag may take place in the center region of the straight portion of a wire bond. The result shows that the deflections of wire sag can be reduced significantly by simply shifting the position of the kink or bend created within a wire bond. Finally, we have concluded that a stacked configuration with smallest bond span may be the preferred selection for the concerns of wire sweep and wire sag issues.

Effects of Bond Pad Thickness on Shear Strength of Copper Wire Bonds

Abstract Copper (Cu) wire bonding is now widely accepted as a replacement for gold (Au), however, its use in high reliability applications is limited due to early failures in high temperature and humid conditions. The Au to Cu wire transition is mainly driven by cost savings though there are other advantages to Cu such as better electrical and thermal conductivity, slower intermetallic compound (IMC) formation and reduced wire sweep during transfer molding. Some automotive, industrial and aerospace industries are still reluctant to adopt Cu wire bonded products due to perceived risks of wire and bond pad cracks, the potential for corrosion, and some lack of understanding about its reliability in harsh conditions. A wire bond is considered good if destructive sampling qualification tests and periodic monitors pass for the batch. Tests include wire pull strength, wire bond shear, IMC coverage, and thickness of bond pad aluminum (Al) remaining beneath the bond. Nondestructive inspections also verify acceptable ball diameter and Al “splash”. This paper focuses on the bond shear test and its contribution to Cu ball bond reliability assessment, especially when changing Al bond pad thickness. A new revision of the JEDEC Wire Bond Shear Test Method, JESD22-B116B, has just been released, to include Cu wirebonds for the first time. It helps to clarify shear test failure modes for Cu ball bonds. However, there are still questions to be answered through research and experimentation, especially to learn the extent to which one may predict Cu ball bond reliability based on shear test results. Pad Al thickness is not considered in the current industry standards for shear test. Yet bond pad Al thickness varies widely among semiconductor products. This research is intended to contribute toward improved industry standards. In this study, power and time bonding parameters along with bond pad thickness are studied for bond strength. Several wire bonds are created at different conditions, evaluated by optical microscope and SEM, IMC% coverage and bond shear strength. Similar bonding conditions are repeated for bond pads of 4um, 1um and 0.5um thickness.

Effect of Minute Bends and/or Kinks of Wire Bond Profile on Sag Deflection for 3-D and Multichip Module Semiconductor Packaging

Wire sag and wire sweep developed during encapsulation process are counted for the lower yield rate of chip packaging in semiconductor industry. For conventional packaging, only one single layer of wire bond was constructed along the perimeter of chip system. The issue of wire sag is not a concern until 3-D and multi-chip modules packaging prevails due to the desperate demands of smaller and faster advanced microelectronics devices. Very few researches have been documented on this subject of sag deflection. An empirical equation based upon major profile parameters of a wire bond has been developed by author to predict sag deflection of ellipse shape wire bond. However, the effect of minute bends and/or kinks of wire bond profile on sag deflection has not been included. In this paper, we investigate three frequently used wire bond loops, ${Q}$ loop, ${S}$ loop, and ${M}$ (modified) loop, to look into these minor characteristics of wire bond profile as compared to bond span and bond height. Based on current results, we find that these minute features may dominate the response of sag deflection of a wire bond.

Wire Sweep Characterization in System-in-Package (SiP) Component with Au Wire Bonding During Epoxy Molding Compounds Molding Process

Wire Sweep Characterization in System-in-Package (SiP) Component with Au Wire Bonding During Epoxy Molding Compounds Molding Process

Wire sweep improvement study of multi-tier palladium–copper wire bonding on low-quad flat package using low-alpha green mould compound

In this paper, a short-shot mould study is performed on device M in order to understand the mould-filling patterns during mould encapsulation. The wire sweep performance is evaluated for two die thicknesses, wire loop heights and various moulding compounds. Moreover, the actual length of worst swept wire is measured using various methods. Designing of experiment with four factors and three centre points is conducted on device M, which is encapsulated with low-alpha compound. The prediction profiles show that reducing the transfer time will reduce the wire sweep percentage. It is also noteworthy that wire sweep performance is strongly related to wire loop height. In addition, a thicker die gives better wire sweep performance as compared to 7 mils die, whereas decreasing the wire loop height decreases the wire sweep percentage. It can be deduced that optimum compound properties, lower wire loop height and optimum moulding parameters are the essential factors that will improve the wire sweep performance during the mould encapsulation process.

The effects of wire geometry and wire layout on wire sweep performance using LQFP packages in transfer mold

Transfer molding is the most effective method for molding encapsulation for semiconductor packaging due to low maintenance cost and high production yield. Wire sweep is a critical moldability issue as excessive wire sweep will contact neighbouring wires, causing electrical short that consequently leads to electrical failure of the package. Wire sweep characterization was carried out with various wire locations, mold flow directions, wire lengths, wire pitches and wire angles on Low Quad Flat Packages (LQFP). JMP statistical analysis was performed to determine the significant factors and correlations of wire sweep performance. It was found that wire length has the most significant correlation with wire sweep percentage. The four wires, two at the bottom-left and top-right (and hence designated as corner 2 and 4, respectively) exhibited the worst wire sweep when the mold gate was located at the top-left corner of the package. The wire sweep performance of seven wire layouts with varying wire lengths were also investigated. The results have revealed and proven that the two wires (corner 2 and 4, respectively) exhibited a higher wire sweep percentage. Overall, it was found that wire X4 has the highest wire sweep deflection.

Fluid/Structure Interaction Investigation in PBGA Packaging

This paper presents experimental and simulation studies of 3-D fluid/structure interaction (FSI) of wire sweep during the encapsulation process of plastic ball grid array (PBGA) packaging in different dies (single and stacked dies). A scaled-up package is fabricated to emulate the encapsulation of PBGA packaging and to study the effects of the FSI phenomenon in the PBGA package. A 3-D model of the mold and wires is created using GAMBIT, and the FSI is simulated using FLUENT and ABAQUS software integrated with mesh-based parallel code coupling interface for the real-time calculations. The effects of the stacked die and inlet pressure of the mold cavity on the melt flow behavior and wire sweep are mainly studied. A constant viscosity of the test fluid is assumed for the experiment. The volume-of-fluid technique is applied for melt-front tracking in the analysis. The numerical results of melt-front patterns and wire sweep are compared with the experimental results and good conformity is found. It is observed that the stacked die significantly influences the melt-front profile and the eventual wire sweep; as the number of dies in the stack increases, the wire sweep also increases.

The wire sag problem in wire bonding technology for semiconductor packaging

Driven by the smaller, faster and cheaper demands of advanced microelectronic devices, the modern packages are required to increase I/O numbers, reduce die and package sizes and lower manufacturing costs. Although, today’s microelectronic devices have many modern types of package, e.g. flip chip, wafer level packaging and tape automated bonding technologies, wire bonding is still the dominant microelectronic packaging technology.To provide more functions within a package, the 3-dimensional and multi-chip modules have come to be the solution of choice in delivering higher integration, smaller and more functional products for meeting consumer requirements, especially in the portable and handheld electrical products.Since the interconnection distance of the multi-chip modules is usually longer than that of a single-chip system, concerns about wire sweep and wire sag for the applications of 3-dimensional packaging technology in the multi-chip module systems have been highly mentioned recently.This has been ascertained by the author in previous studies, the longer the bond length and the higher the bond height of a wire bond, the smaller the sweep stiffness of the bond system becomes. The lower sweep stiffness of the wire bond will always cause higher risk of wire sweep. Consequently, for 3-dimensional and multi-chip packaging, excessive wire sag can lead to wire touch in the lower layer and thereby causing short circuits and malfunction of chips.Wire sag problems are very crucial to the applications of 3-dimensional and multi-chip packaging in semiconductor industry. To authors’ knowledge, this issue has never been investigated. The main purpose of this paper will be to study in depth the wire sag problem for long wire bonds, applied in 3-dimensional and/or in multi-chip module packaging. A definition of the sag stiffness of a wire bond will be shown to represent sag resistance of specific profiles of wire bond. The author will also present wire sag experiments of wire bonds thereby verifying numerical analysis.

FSI Simulation of Wire Sweep PBGA Encapsulation Process Considering Rheology Effect

This paper presents a 3-D fluid-structure interaction (FSI) technique using mesh-based parallel code coupling interface (MpCCI) for the visualization of wire sweep during encapsulation of the plastic ball grid array packaging, considering the polymer rheology effect. In the molding process, the encapsulant flow behavior is modeled by the Castro-Macosko viscosity model including the curing effect and volume of fluid technique for melt-front tracking. The viscosity model is written in C language and compiled using user-defined functions into the FLUENT analysis. Wire sweep behavior is analyzed by ABAQUS and integrated with FLUENT software by MpCCI as an interface of fluid and solid interaction. Three types of epoxy molding compound (EMC), namely, Cases 1-3, were utilized for the study of fluid flow inside the mold cavity. The melt-front profiles and viscosity versus shear rate for all cases are analyzed and presented. The degree of conversion of the molding compound during the encapsulation process at the top view of the package for different EMCs is also studied. Pressure distribution around the wire region and wire sweep profiles within the mold are presented. The numerical results of the melt-front behavior and wire sweep are compared with the previous experimental results and found in good conformity. In the present case, Case 2 with a lower viscosity shows lower air trap, lower pressure distributions, and lower wire deformation. Therefore, the strength of MpCCI in handling FSI problems is proven to be excellent. The work presented in this paper is expected to be a reference and guide for the microelectronics industry.

Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-k materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 μm) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (-40°C to 125°C) and high temperature storage (HTS at 150°C) for 1000 h.

Chip Card Globe Top Module Robustness Study

Usage of security smart card is growing rapidly in recent electronic world. Unquestionably in the next decade, each individual would need at least one smart card to store and secure his or her confidential information for daily application. Therefore the robustness of chip card module plays the most important role in the smart card application. This paper discusses about the robustness of Globe Top (GT) Module through a complete qualification flow which includes module level and card level reliability tests. The objective of this qualification is to prove the quality of current GT module manufactured in house for market application. Basically in this study, two modules type namely Memory M3.2-SLE55XX and Controller M5.1-SLE66XX had been selected. These two modules coupled with two types of glass epoxy (FR4) tape were evaluated. Internal assembly level reliability data including die shear, wire ball size, wire ball height, wire pull, ball shear, loop height, wire sweep, encapsulation dam & fill dimension and thickness were collected and analyzed. Meanwhile reliability tests for modules level and card level which include thermal, climatic, chemical and mechanical resistance were tested. Reliability results revealed that these two packages passed the entire qualification requirements and proven to be robust for smart card application.

Simulation and experimental analysis of large area substrate overmolding with epoxy molding compounds

This paper presents new experimental and numerical methods to characterize the transfer overmolding of substrates with epoxy polymer. We investigated Multi Chip Modules on ceramic panels as well as on printed circuit boards encapsulated as a Mold Array Package (MAP). Experiments show that the polymer flow during the overmolding process depends significantly on the mold height: While standard MAP-type mold cavities are filled homogeneously and symmetrically in most cases, low cavity heights (<500 μm) can cause the flow front to concentrate on a few flow paths (flow front fingering). We developed a numerical method to describe this inhomogeneous polymer flow. The reason for flow front fingering seems to be local variations of polymer viscosity which enforces a necking on distinct flow paths. Fingering can cause the formation of air traps and excessive wire sweep. We also developed new experimental methods to measure the pressure distribution within cavities: our sensor is based on commercially available, passive pressure sensitive films from FUJUFILM and is operational at temperatures up to 180°.

Fine and ultra‐fine pitch wire bonding: challenges and solutions

Purpose – The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.Design/methodology/approach – Dozens of journal and conference articles published recently are reviewed.Findings – The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.Research limitations/implications – Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.Originality/value – This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.