Wire Package Research Articles

Static properties analysis of fiber optic wire wrapping

To improve the quality of fiber optic wire wrapping, the influence of each parameter of fiber optic wire wrapping on the stress distribution of wire wrapping is studied, and the mechanical properties of fiber optic wire wrapping are simulated based on the principle of fine mechanics of composite materials. Solid elements are used for modeling through finite element analysis, and the problem of using ANSYS to solve the wire package is initially solved by establishing a 1° model for analysis and calculation. The results show that the core cylinder slightly, core cylinder radius, and fiber diameter have no effect on the stress distribution state of the fiber in the wire pack, but if the core cylinder stiffness increases, the minimum stress value of the wire pack will also increase, and the minimum stress area of the fiber unit tends to be far from the core cylinder surface.

The Influence of Wire Diameter Uniformity on the Quality of Fiber Optic Wire Package

The fiber optic wire package is the core component of fiber optic guided rockets. Due to the non-uniformity of the fiber optic wire diameter, the winding process is prone to winding defects, which affects the missile launch process. In this paper, a finite element simulation model for the winding process of the fiber optic wire package is established. The accuracy of the simulation model is verified by comparing it with the analytical model for the contact pressure between fiber optic layers. Then finite element models considering the wire diameter tolerance are established to analyze the effect of diameter uniformity on the winding quality of the fiber package. The results show that the stress distribution of a fiber optic package becomes increasingly uneven with increasing wire diameter non-uniformity, and the structural stability of the package decreases. The edge fibers of a 20-layer optical fiber package are easily extruded when the deviation from the nominal diameter is more than 3%. This study helps to guide the manufacturing accuracy of optical fibers and improve the structural stability of the wire package.

Numerical simulation of brush seal tests

A numerical analysis of deformation of the brush seal wire package as part of dynamic rotor&stator system of gas turbine engines is describes. The estimated definition of the reaction force of the brush package is based on solving the contact problem of the interaction of bristles with each other, with the rotor and the rear plate of the seal case, taking into account the action of the distributed gas flow pressure. Comparison of the results obtained with the data of well-known estimated and experimental studies. According to the results of calculations, it was noted that the accounting of the spatial contact interaction of the elements of the brush seal significantly affects on reaction force value and, accordingly, on the brush package rigidity. In the presence of a gas pressure drop on the compaction, the results of calculations on a simplified half-analytical model based on the analysis of the deflection of one bristles according to the model of the flat bending of the console straight beam, and the spatial model differ in order. It is necessary to take into account this effect when calculating the wear of the brush seal and the forecast of its effectiveness with the course of operation. A characteristic feature of the dependence of the reaction of the brush package from the magnitude of the rotor displacement is the presence of hysteresis in the "load - unloading" cycle due to friction in the system. The impact of gas flow on the bristles significantly increases the scope of hysteresis loops and changes its shape. On the scale of the loop also strongly affects the coefficient of friction pair "schedules - rotor". The obtained dependences of the reaction of the brush package from the magnitude of the tension / displacement of the rotor (hysteresis loops) allow you to clarify the calculated mathematical model of the brush seal after testing on the stand.

Advanced Manufacturing of Printed Melt Wire Chips for Cheap, Compact Passive In-Pile Temperature Sensors

Melt wires are a passive sensor used to determine peak temperatures. Traditional melt wires are commonly used in test reactor experiments, such as in the Advanced Test Reactor. However, the conditions within a reactor present significant challenges towards test design, due to space limitations and the harsh environment. For example, some test capsules have only a couple millimeters in diameter available for instrumentation, which is too small to accommodate a traditional melt wire package. To enable instrumentation for space-limited applications, peak temperature sensors have been developed using additive manufacture to form printed melt wires. This paper reports on the design and fabrication of miniaturized melt wire chips with printed melt wires. This study advances the development of unique, compact temperature sensors capable of sensing user specified temperature ranges within the harsh environment of irradiation testing.

Reliability of Fine-Pitch <5-μm-Diameter Microvias for High-Density Interconnects

Downscaling of package wiring has been the singular focus to achieve higher logic-memory interconnect density to meet next-generation needs for high-bandwidth computing. This article presents, for the first time, a systematic modeling and experimental study of sub-5- $\mu \text{m}$ -diameter microvia reliability. Geometry design considerations and build-up dielectric material properties in evaluating the microvia fatigue life are investigated. Finally, experimental thermal-cycling reliability results of sub-5- $\mu \text{m}$ -diameter microvias are correlated with the modeling results.

Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board

A chip-to-chip active noise coupling demonstrator integrates two identical complementary metal oxide silicon (CMOS) chips on a printed circuit board (PCB), where each chip has the capability of power noise generation by CMOS shift resister array circuits (noise source; NS) and also power noise measurements by on-chip voltage monitoring circuits (OCM). For establishing the noise aware design strategy and methodology, a full-system level noise coupling simulation technique is evaluated on the demonstrator representing a multi-chip mixed-signal PCB. In an experimental scenario, an IC chip (Aggressor IC) operates the NS to generate power noise and the OCM measures the voltage fluctuation of the power delivery network (PDN) within the chip. On the other hand, another IC (Victim IC) holds the NS in no operation while uses the OCM to monitor its PDN voltage fluctuation caused by the conducted noise from the aggressor IC. For the verification of simulation accuracy, two chip power models (CPM), package wire models, discrete de-cap models and a single PCB model are combined into a chip-package-system (CPS) integrated model. The simulation was performed in about 2 hours for CPS integrated noise simulation including S-parameter extraction of the PCB. It is demonstrated that the full-system model with the two CPMs successfully simulates chip-to-chip active noise coupling, namely noise propagation from internal circuits of an aggressor chip to those on a victim chip. The chip-to-chip noise coupling simulation exhibited good agreements with measurements in case studies. The simulation methodology enables conductive noise aware design for multi-chip mixed-signal PCB in its design stage.

Novel Decapsulation Method for Silver-Based Wire-Bond Semiconductor Packages With High Reliability Using Mixed Salt–Acid Chemistry

Decapsulation of Ag wire packages has gained a plethora of interest due to the replacement from Au wire packages to Ag wire packages recently and to the lack of optimization on its process. This paper presents a novel decapsulation recipe for Ag wire packages using mixed salt–acid chemistry that is applicable for industry standard needs that performs decapsulation at high temperature of 240 °C within several seconds. This method serves to decapsulate the Ag wire packages selectively, leaving the Ag wires intact.

Luminous Efficiency of Pd-Doped Ag-Alloy Wire Bonded LED Package after Reliability Tests

In this study, binary Ag-alloy wires were doped with different Pd concentrations, and each wire was encapsulated in an LED package. The initial optical characteristics were tested, and reliability was tested with the high temperature storage life (HTSL), high temperature operating life (HTOL) and wet high temperature operating life (WHTOL). The luminous efficiency of the Ag-alloy wire LED package was about 2% higher than that of the Au wire package, but the addition of 6% Pd to the Ag-alloy wire decreased the luminous efficiency to close to that of the Au-wire LED package. This was due to the high reflectivity of silver in the blue wavelength region, as compared to the low reflectivity of palladium. After 1,000 hours of HTOL and WHTOL, the results showed that the performance of luminous flux maintenance increased with increasing Pd content, indicating that Ag-alloy wires doped with a sufficient amount of Pd can inhibit degradation due to oxidation reaction and thermal and humidity aging. Therefore, binary Ag-Pd alloy wires produced with specific drawing and annealing processes are suitable for mid-power white light LEDs in lighting applications.

Swing Touch Risk Assessment of Bonding Wires in High-Density Package Under Mechanical Shock Condition

Long bonding wires may swing significantly and touch with adjacent ones, which will result in short circuit under mechanical condition, especially in aerospace applications. This may seriously affect the operational reliability of high-density hermetic package components. The aim of this paper is to assess the touch risk of high-density package component under mechanical shock condition. An experiment setup, which can obtain the touch critical load and detect the wires swing touch through voltage signal captured by oscilloscope, is designed and built. To obtain the vibration data of different bonding wire structures under different shock loads, numerical simulation models are established after verified by the experimental data. Additionally, initial swing amplitude model, vibration frequency model, and damped coefficient model are established based on the simulation and experiment data. Furthermore, wire swing touch risk assessment model is established in consideration of the distribution of wire structure and shock load deviation. Based on the verified numerical simulation model, vibration characteristic parameters, including the initial swing amplitude, vibration frequency, and damped coefficient, can be calculated by numerical simulation and experimental results. The proposed method can be used to assess bonding wire touch risk in high-density hermetic package quantitatively. Potential touch risk, which cannot be reflected by failure analysis of structure damage after test, can also be detected by the electronic measurement designed in this paper. The proposed method can effectively reflect short circuit between long bonding wires of hermetic package in large shock applications, such as transport and launch.

Study on micromixing and reaction process in a rotating packed bed

The exploration on the microscale transport phenomena is of great significance to understand the mechanism of microscale mixing and chemical reaction in a rotating packed bed (RPB). In this paper, numerical investigation is carried out and compared with the experimental results. Two different scale reaction models are applied to simulate and the numerical result is in reasonable agreement with the experimental results. The fluid flow and the species transfer with a competitive and consecutive reaction are studied to obtain the evolution of the segregation index and flow field. Each environment changes and is updated continuously with the liquid film flowing outward, and the micromixing and reaction are influenced by the fractions p1 and p2 of different environments. It is evidenced that different factors such as rotational speeds, volume ratios and initial mixing concentration impose considerable influences on the micromixing and reaction processes. The micromixing time ranges about 5.2×10−2–1×10−3ms showing that micromixing performance in RPB is much better. The main product and by-product appear different evolution pattern along the package wires, which provide guideline for the optimization of RPB structure. The optimization on the RPB structure is provided and the simulation results clarify a deeper understanding on the micromixing and reaction features in RPB.

Investigation of single and double pass solar air heater with transverse fins and a package wire mesh layer

The purpose of this work is to construct and test single-pass and double-pass solar air heaters (SAHs) with four transverse fins. These fins were painted dark black and placed transversely to create four equal-spaced sections. Sixteen steel wire mesh layers were located between these fins as an alternative to an absorber plate; they had a cross-sectional area of 0.18cm×0.18cm and an internal diameter of 0.02-cm. In this project, the thermal efficiency and outlet temperature were studied in a geographic area located in the city of Famagusta, North Cyprus. The experimental results indicate that the thermal efficiency increases as the air flow rate increases for the range of (0.011-0.032)kg/s. The maximum efficiency obtained using the 7.5-cm high collector was 62.50% for the double-pass SAH and 55% for the single-pass SAH at an air flow rate of 0.032kg/s. Moreover, the thermal efficiency further increases by decreasing the height of the lower air pass of the double-pass SAH. The difference between the inlet temperature and outlet temperature, ΔT, indicated an inverse relationship with air flow rate: ΔT increased as the air mass flow rate decreased. The maximum differences (ΔT) observed were 45.30K for the double-passes SAH and 39.9K for the single-pass SAH at 0.011kg/s, which were recorded during the middle of the day with a maximum solar intensity. The results demonstrate a significant improvement in the thermal efficiency and outlet air temperature.

내부 고조파 조정 회로로 구성되는 고효율 370 W GaN HEMT 소형 전력 증폭기

본 논문에서는 내부 고조파 조정 회로로 구성되는 셀룰러와 L-대역용 소형의 고효율 370 W GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) 소형 전력 증폭기(PA)를 구현하였다. 원천 및 2차 고조파 주파수에서 동시에 높은 효율을 내기 위해 새로운 회로 정합 형태를 적용했다. 소형화를 위하여 새로운 41.8 mm GaN HEMT와 2개의 MOS(Metal Oxide Semiconductor) 캐패시터를 구성 물질의 변화를 이용하여 열 저항을 개선한 <TEX>$10.16{\times}10.16{\times}1.5Tmm^3$</TEX> 크기의 새로운 패키지에 와이어 본딩으로 결합하였다. 드레인 바이어스 48 V 인가 시, 개발된 GaN HEMT 전력 증폭기는 370 W 포화 출력 전력(Psat.)과 770~870 MHz에서 80 % 이상, 1,805~1,880 MHz에서 75 % 이상의 드레인 효율(DE)을 나타내었다. 이는 지금까지 보고된 셀룰러와 L대역에서 GaN HEMT 전력 증폭기 중 최고의 효율과 출력 전력 특성이다. In this paper, a compact 370 W high efficiency GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) power amplifier(PA) using internal harmonic manipulation circuits is presented for cellular and L-band. We employed a new circuit topology for simultaneous high efficiency matching at both fundamental and 2nd harmonic frequency. In order to minimize package size, new 41.8 mm GaN HEMT and two MOS(Metal Oxide Semiconductor) capacitors are internally matched and combined package size <TEX>$10.16{\times}10.16{\times}1.5Tmm^3$</TEX> through package material changes and wire bonded in a new package to improve thermal resistance. When drain biased at 48 V, the developed GaN HEMT power amplifier has achieved over 80 % Drain Efficiency(DE) from 770~870 MHz and 75 % DE at 1,805~1,880 MHz with 370 W peak output power(Psat.). This is the state-of-the-art efficiency and output power of GaN HEMT power amplifier at cellular and L-band to the best of our knowledge.

Formation and Growth of Intermetallics in an Annealing-Twinned Ag-8Au-3Pd Wire Bonding Package During Reliability Tests

Wire bonding on Al pad packages with an innovative annealing twinned Ag-8Au-3Pd alloy wire results in a sufficient interfacial intermetallic layer at the initial as-bonded stage, while its growth during the further temperature cycling test and pressure cooker test is very slow. Even after prolonged high-temperature storage at 150°C for 500 h, the thickness of its intermetallics is only around 1.7 μm. In contrast, a very thin CuAl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> intermetallic layer appears at the interface of the Pd-coated Cu wire bonded package, and a thick layer of Au <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> intermetallic compounds forms in the Au wire package, which grows to a thickness of around 4.0 μm after high-temperature storage at 150 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C for 500 h. Energy dispersive X-ray spectrometry analyses indicate that AgAl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , Au <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and CuAl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are the main intermetallic phases formed in the packages bonded with Ag-8Au-3Pd, and Au and Pd-coated Cu wires, respectively. However, an additional Pd-containing Ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Al layer found at the AgAl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al interface of Ag-8Au-3Pd wire bonded package can interrupt its intermetallic reaction, and the annealing twins can further slow the intermetallic growth.

Digital Processing of Single-Carrier Cyclic Prefixed Frequency Channelized Receiver for Serial Links

The achievable data rates in modern serial-link systems are limited by the intersymbol interference (ISI) caused by wire losses and package parasitics. Although more sophisticated digital communication techniques can be used to combat ISI, the lack of available multibit analog-to-digital converters (ADCs) has primarily limited their use. A promising approach to relax the ADC requirements so as to enable Nyquist-rate digitization is to channelize the received signal into multiple frequency subbands and then sample using a bank of low-frequency ADCs. In this brief, the digital processing required in such a channelized receiver is presented. The use of single-carrier cyclic prefixed communication is also proposed to reduce the computational complexity in channels with moderate-to-large ISI.

Production process options for IC package wire sweep in view of the matter element theory

The problematic wire sweep in the IC production bonding process acts as the 1st layer structure is a factor that critically affects product quality. Among the factors affecting IC packaging numerous contradictory interactions occur. The said influence is more significant due to the increasing number of IC lead legs and smaller package sizes. In this research, the Matter Element Model is adopted to implement Design of Experiment to reduce the possibility of wire sweep for various production process options. The Matter Element Model algorithm is adopted to attain the optimal results in the partial production process. The production process is examined using Computer-Aided Simulations; thus, the time spent for systematic experimental analysis is shortened for all available options.

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous technologies and to support robust manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density I/O interconnection can enable tight integration of heterogeneous technologies which approximate the performance of an integrated system-on-chip with a virtual chip using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density microbump interconnections scale to smaller size. In addition to heterogeneous integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Process and design analysis for ultrafine-pitched wiresweep elimination in advanced copper heat spreader BGA package

The semiconductor device trend for increasing functionalities and performances yet with smaller overall feature sizes presents escalating obstacles to the decreasing form factor along with demanding thermal carrying capability required at the package level. To confront this compounding issue, ultrafine-pitch wirebond interconnect coupled with thermally enhanced copper heat spreader attached to the package are introduced. However, the additional copper heat spreader thickness introduced within the package challenges the design of the package's wire, its loop height, and the molding process control to prevent wire sweeping occurrences. This study investigates the impact of different ultrafine pitched wire types, wire loop designs, copper heat spreader structures, and mold material types on eliminating device short from occurring due to the wire sweeping phenomena. A full factorial experiment is performed using an active silicon device packaged in a thermally enhanced ball grid array (BGA) test vehicle. In addition, test characterization is carried out using x-ray and multiinsertions hot/cold continuity tests. Then, a detailed failure analysis is performed by package decapsulation and scanning electron microscopy/energy-dispersive x-ray (SEM/EDX) to confirm the experimental findings. In conclusion, the study finds that for an ultrafine-pitched thermally enhanced BGA package, wire type is insignificant to reduce wire shorting occurrences. However, mold material and copper heat spreader structure using an optimized wire loop design are significant factors in eliminating wiresweep shorting phenomena. This study concludes with a wirebond interconnect and heat slug design recommended along with an improved process parameters and assembly material sets found from the experiment.

Prediction of Wire Sweep During the Encapsulation of IC Packaging With Wire Density Effect

More wires in a package and smaller wire gaps are the trend in the integrated circuit (IC) packaging industry. The effect of wire density is becoming increasingly apparent, especially on the flow pattern of the epoxy molding compound during the molding process and, hence, on the amount of wire sweep. In most mold flow simulations, the wire density effect is ignored. In order to consider the wire density effect on the predicted amount of wire sweep in the analysis, several indirect approaches were used by researchers before. But those approaches were not general enough to be applied to all cases. This paper presents a more direct and convenient approach to consider wire density effect by including wires in the mesh model for three-dimensional (3D) mold-filling analysis. A thin small outline package (TSOP) with 53 wires is used as the demonstration example, and all the wires are modeled in the 3D mesh. By comparison with experimental results, it is shown that this approach can accurately describe the wire density effect. When the wires are included in the mesh model, the predicted wire sweep results are better than those without considering the wire density effect.

実験計画法を用いたボンディングワイヤループ形状適正化の検討(J01-4 最適構造設計,J01 エレクトロニクス実装における熱制御および信頼性評価)

A method for evaluating fatigue life of the bonding wires in semiconductor packages under a temperature cycling test was studied analytically using a finite element method based on design of experiments. The sensitivity analysis of the maximum strain occurs in a bonding wire was carried out to make clear the effect of the loop-shape of the wire on the strain. It was found that we can evaluate the fatigue life of a bonding wire under various conditions of a temperature cycling test at the early stage of design by using both the Chebyshev function of a loop, shape factor and the Manson-Coffin fatigue life curve. It was also found that highly reliable loop shape of the wire can be designed by minimizing the strain using design of experiments.

RF SAW filter package design for wireless communications

AbstractThis paper describes a new method to design a ceramic chip and wire package for an RF SAW filter. Both the solid model of the package and bond wires are included in the full‐wave analysis. A novel port configuration is used in finite‐element simulation. Agreement between measurement and simulation is found to be excellent. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 39: 399–401, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11229