Increase In Wirelength Research Articles

Experimental and Numerical Investigation of Electromigration Behavior of Printed Silver Wire Under High Current Density

Abstract The electromigration (EM) damage is becoming a severe problem in the printed flexible electronics as the printed circuits are fabricated thinner and thinner due to the development of printing technology. In this work, the EM behavior of printed silver wires was investigated by EM experiments and numerical simulations. The EM tests showed that voids are generated in the cathode area and hillocks are formed in the anode area for a wire with a small length. However, with the increase of wire length, hillocks tend to occur on the two sides of the silver wire middle part. The results of numerical simulations based on the atomic flux divergence (AFD) method revealed that the formation of the hillocks on the printed wire is caused by not only the mechanism of electron wind but also the strong temperature gradient along the wire length and width direction. Also, it can be concluded that the temperature gradient induced by Joule heating plays a more important role than electron wind in the atomic migration of the printed silver wire subjected to a high current density. The influence of the printed silver wire size on the EM behavior was also analyzed by numerical simulation, and the results demonstrated that the printed silver wires with a larger length and a smaller width-to-thickness ratio are more likely to develop hillocks on the two sides of silver wire middle part while subjected to a high current density.

Polarity-controlled AlN/Si templates by in situ oxide desorption for variably arrayed MOVPE-GaN nanowires

In this paper, we present a comprehensive study of position-defined Al-polar AlN nucleation on lithographically patterned Si(111) substrates as a method to obtain ordered Ga-polar GaN nanowire arrays, with possible application in future nanowire-based devices such as LEDs and photoelectrochemical water-splitting cells. In a hydrogen processing step, ex situ prepared oxide on pre-structured Si-pillars could be selectively removed. This enabled Al-polar AlN nucleation on the Si-pillar’s sidewalls during the following metal–organic vapor phase epitaxy, while dominant N-polar AlN layer growth was observed on the still oxidized Si(111) horizontal substrate surface neighboring the pillars. 100% of the Ga-polar GaN wires are emerging on the Al-polar AlN growth sites, thus selective area epitaxy without any mask material could be realized. To gain a precise understanding of the growth mechanisms, the attainable Ga-adatom collection area per NW was varied by changing the Si-pillars’ placement pattern. The wire length and diameter increase with extended pitch. At a constant pitch, the size of the wires is adjustable by variation of the Si-pillars’ diameter, therefore growth of GaN wires of controllable dimension and pitch could be attained. Additionally, parasitic NW growth was completely suppressed for any pitch < 3.5 µm, while an increased pitch resulted in additional parasitic growth. Based on these results a model was derived, which includes the site-controlled removal of the oxide, the thus achieved local polarity control of AlN growth, and the influence of the collection area of each NW with respect to their size, whereas the collection area could be set in the experiment by adjustment of the lithographically controlled pitch and growth-parameter dependent Ga-adatom diffusion length. The mask-less polarity- and site-controlled growth of NWs with a height of 5.3 µm ± 0,33 µm and a diameter of 800 nm ± 160 nm at a pitch of 2.5 µm could be attained. Hence, a deep understanding of the growth mechanisms and the geometrical control of polarity- and site-controlled GaN NWs could be achieved, forming the base for development of NW-based devices on a conductive AlN/Si-template.

Hydrodynamic Efficiency of Floating Breakwaters WITH Plates (Dept.C)

The efficiency of the floating breakwaters was experimentally studied under normal and regular waves with wide ranges of wave heights and periods. The efficiency of the breakwater is presented as a function of the transmission, reflection, and dissipation coefficients. Different parameters affecting the breakwater efficiency such as, the connection of the virtical plates under the floating body at different positions, length of mooring wires and the wave length were tested. It was found that, the transmission coefficient decreases with the increase of relative breakwater width (B/L), the number of plates and also with the increase of the relative wire length (l/h) whereas the reflection coefficient takes the opposite trend. In addition, the suggested floating breakwater system dissipates about 15% to 30% from the incident wave energy. Also, the suggested floating breakwater model is efficient compared with other types of pontoon breakwaters.

Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits

While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are TSVs that facilitate heat transfer across stacked dies without carrying signal and provide a potential thermal management solution to 3-D ICs. However, the use of TTSVs increases the distance between IC blocks and signal delay. The trade-off between temperature and wirelength is difficult to avoid in TTSV-integrated 3-D ICs. Here, we present a hierarchical approach to optimize the floorplan of a 3-D Nehalem-based multicore processor via simulated annealing (SA). Our simulations show that an increase in the TTSV area accompanies a decrease in peak temperature but the wirelength strongly depends on the TTSV placement, which is uniquely optimized for each case of the allowed TTSV area. Compared to the floorplan with a fixed TTSV placement that places TTSV between cores, our algorithm optimally places TTSVs between IC blocks and finds an optimal floorplan with the minimum cost of peak temperature, wirelength, and area at 6% TTSV area overhead. The peak temperature is reduced from 116 °C to 100 °C with only a 3.5% increase in wirelength. Our floorplan optimization method can provide effective thermal management solutions to 3-D ICs.

Compensatory Mechanisms in Temperature Dependence of DNA Double Helical Structure: Bending and Elongation.

Changes in the structure of double-stranded (ds) DNA with temperature affect processes in thermophilic organisms and are important for nanotechnological applications. Here we investigate temperature-dependent conformational changes of dsDNA at the scale of several helical turns and at the base pair step level, inferred from extensive all-atom molecular dynamics simulations of DNA at temperatures from 7 to 47 °C. Our results suggest that, contrary to twist, the overall bending of dsDNA without A-tracts depends only very weakly on temperature, due to the mutual compensation of directional local bends. Investigating DNA length as a function of temperature, we find that the sum of distances between base pair centers (the wire length) exhibits a large expansion coefficient of ∼2 × 10-4 °C-1, similar to values reported for thermoplastic materials. However, the wire length increase with temperature is absorbed by expanding helix radius, so the length measured along the helical axis (the spring length) seems to suggest a very small negative thermal expansion coefficient. These compensatory mechanisms contribute to thermal stability of DNA structure on the biologically relevant scale of tens of base pairs and longer.

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a -35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show -50.1% area reductions with -0.3% wirelength reductions and -18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning

Redundant via (RV) insertion helps prevent via defects and hence leads to yield enhancement. However, RV insertion in self-aligned double patterning (SADP) processes is challenging since cut optimization has to be considered together. In SADP, parallel one-dimensional metal lines are divided into signal wires and dummy wires by line-end cuts. If an RV is inserted, signal wires need to be extended to connect to the RV. To this end, an additional cut, which we call RV cut, is introduced to make a space for the extension. Since RV cuts and line-end cuts are manufactured with the same mask set, design rules between those cuts have to be honored, which incurs proper distribution and mask assignment to individual cuts. In this article, we address a problem of integrated RV insertion and cut optimization. We show that the problem can be formulated as an integer linear programming (ILP). We also propose a heuristic algorithm is presented for practical application, in which potential locations of RVs are first identified and used to properly insert as many RVs as possible while minimizing the conflict between RV cuts. Our experimental results demonstrate that 75% of vias receive RVs with 8% increase in total wire length, which is only slightly worse than the optimal result obtained by ILP.

Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs

Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.

The length and hydrogenation effects on electronic transport properties of carbon-based molecular wires

Abstract It is known that the conductance of a wire decreases linearly with the increase of its length in the macro circuit. But things are different in mesoscopic field, especially in molecular dimensional circuits due to the quantum interferences in molecular size. In this work, first principles is used to investigate how wire length and hydrogenation degree influence the conductance of molecular wires. For comparison, two types of carbon-based molecular wires, single carbon atomic wire and phenyl ring wire with single hydrogenation or dihydrogenation, are chosen and coupled to two zigzag graphene nanoribbon electrodes, respectively. We show that the conductance of zigzag carbon atomic wire with single hydrogenation exhibits an evident even-odd oscillatory behavior with the increase of wire length, while that of phenyl ring wire starts to increase before decreasing. However, when the above types of wires are edged with dihydrogenation, their conductance decreases exponentially with the increasing wire length. In addition, fine current rectification is found in asymmetric phenyl wires induced by hydrogenation degree, which can be used as diode in future molecular devices. Analyses via orbital hybridization, transmission path, HOMO-LUMO position and so on reveal the microscopic mechanism of the above interesting results.

Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs

In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic 3-D (M3-D) ICs across different technology nodes. Our studies show that PDN worsens routing congestion more severely in M3-D ICs than in 2-D designs due to the significant reduction in resources for 3-D connections. The relative impact worsens at advanced technology nodes due to higher congestion of interconnects. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues further in 3-D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in M3-D ICs than through silicon via-based 3-D and 2-D designs because of the higher integration density and the severe competition between signal and power connections. We also compare the impact of PDN on full chip routing in M3-D ICs versus face-to-face 3-D ICs. Lastly, we use various PDN design optimization techniques for M3-D ICs at different nodes and obtain up to 13.9% signal wirelength and 17.6% total power reduction under the given IR drop budget.

Power-Driven Global Routing for Multisupply Voltage Domains

This work presents a method for global routing (GR) to minimize power associated with global nets. We consider routing in designs with multiple supply voltages. Level converters are added to nets that connect driver cells to sink cells of higher supply voltage and are modeled as additional terminals of the nets during GR. Given an initial GR solution obtained with the objective of minimizing wirelength, we propose a GR method to detour nets to further save the power of global nets. When detouring routes via this procedure, overflow is not increased, and the increase in wirelength is bounded. The power saving opportunities include (1) reducing the area capacitance of the routes by detouring from the higher metal layers to the lower ones, (2) reducing the coupling capacitance between adjacent routes by distributing the congestion, and (3) considering different power weights for each segment of a routed net with level converters (to capture its corresponding supply voltage and activity factor). We present a mathematical formulation to capture these power saving opportunities and solve it using integer programming techniques. In our simulations, we show considerable saving in a power metric for GR, without any wirelength degradation.

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization

In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.

One-step molten-salt synthesis of BaTi4O9 nanowires with oxygen deficiency-enhanced dielectric performance

One-dimensional nanostructures of BaO-xTiO2 binary oxides with a high oxygen deficiency and a good dielectric performance are of great interest but seldom studied. In the present study, single-crystalline BaTi4O9 (stoichiometric BaO–4TiO2) nanowires were synthesized using a simple, one-step molten-salt method by co-heating the powder mixtures of NaCl, TiO2 and BaCl2 nanoparticles at 750 °C. A series of spontaneous processes in the molten NaCl/BaCl2 salt mixture with the dispersed TiO2 nanoparticles, including ion diffusion, chemical reaction, particle agglomeration and ion exchange, yielded the BaTi4O9 nanowires. Photoelectron spectroscopic and dielectric analyses indicated that a high fraction of oxygen deficiency for 10.4% provided the as-synthesized BaTi4O9 nanowires with a high capacitance density of 13 F/m2. Thermal annealing lowered the oxygen deficiency to 6.6% and the capacitance density to 9 F/m2. The increase in wire length increased the oxygen deficiency and dielectric constant of the nanowires.

Voltage Island Partitioning Based Floorplanning Algorithm

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction

We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits without appreciable increase in wire length (WL). FlowPlace includes: 1) a timing-driven (TD) analytical global placer TAN that uses accurate pre-route delay functions and minimizes a combination of linear and quadratic objective functions; 2) a discretized network-flow-based detailed placer DFP that has new and effective techniques for performing TD/WL-driven incremental placement while satisfying row-width (white space) constraints; 3) new and accurate unrouted net delay models that are suitable for an analytical placer; and 4) an effective probability-based WL-cost function in detailed placement for reducing WL deterioration while performing TD-incremental placement. We ran FlowPlace on three sets of benchmarks with up to 210 K cells. Starting from WL-optimized placements done by Dragon 2.23, and using purely timing-driven incremental placement, we are able to obtain up to 33.4% and an average of 17.3% improvement in circuit delays at an average of 9.0% WL increase. When incorporating both timing and WL costs in the objective functions of global and detailed placement, the average WL increase reduces to 5.8%, a 35% relative reduction, while the average delay improvement is 15.7%, which is only relatively 9% worse. The run time of our incremental placement method is only about 10% of the run time of Dragon 2.23. Furthermore, starting from an already timing-optimized placement done by TD-Dragon, we still obtain up to 10% and an average of 6.5% delay improvement with a 6.1% WL deterioration; the run time is about 6% of TD-Dragon's.

Robust Chip-Level Clock Tree Synthesis

Chip-level clock tree synthesis (CCTS) is a key problem that arises in complex system-on-a-chip designs. A key requirement of CCTS is to balance the clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. Achieving this is difficult because the clock trees in different IPs might be vastly different in terms of their clock structures and cell/interconnect delays. The chip-level clock tree is expected to compensate for these differences and achieve good skews across all corners. Also, CCTS is expected to reduce clock divergence between IPs that have critical timing paths between them. Reducing clock divergence reduces the maximum possible clock skew in the critical paths between the IPs and thus improves yield. This paper proposes effective CCTS algorithms to simultaneously reduce multicorner skew and clock divergence. Experimental results on several test-cases indicate that our methods achieve 30% reduction in the clock divergence with significantly improved multicorner skew variance, at the cost of 2% increase in buffer area and 1% increase in wirelength.

Modeling the interface effect of shape memory alloy composite materials

PurposeThe purpose of this paper is to investigate the stress distribution in shape memory alloy (SMA) composite due to phase transformations in the fiber in view of the applied boundary conditions on the matrix.Design/methodology/approachA consistent homogenization of a SMA wire‐reinforced polymer composite volume element undergoing quasi‐static deformation was performed and SMA wire‐matrix interface behaviour was presented. For the SMA wire, a one‐dimensional phenomenological constitutive model was used. Eshelby's inclusion theory was employed for homogenization. A strain averaging approach was reviewed in which the average strain was substituted back to obtain the expressions for the effective stiffness, the inelastic strain, and the average stresses in the constituent phases. In order to study the stress distribution in SMA composite and constituent phases (fiber and matrix) as a consequence of the SMA wire‐matrix interface effect, interfacial stress model was derived. Interfacial axial and shear stress distribution is characterized for forward and reverse phase transformations. Finally, the thermomechanical behaviours were computed by applying strain energy approach incorporating the interface effects.FindingsThe results presented show that due to the difference between the shear modulus of matrix and SMA wire, and because of the strain non‐uniformity at the SMA wire‐matrix interface, shear stress is developed within the matrix under the axial loading of the representative volume element (RVE). The shear stress increases more rapidly as the SMA wire radius is increased but not with increase in the length. However, the axial stress does not increase much with increase in the SMA wire radius and length. Further, the average stress equation of the RVE at the SMA wire‐matrix interface is effectively addressed. The modeling approach is successfully validated extensively for different geometric and volumetric parameters for different loading conditions. It is evident that the interface effect of SMA wire composites is SMA stiffness dominated due to the fact that the geometric parameters do not influence much the stresses as compared to the change in SMA wire stiffness.Originality/valueThe approach is based on modeling the fiber matrix interface effect using homogenization scheme. Further, the strain energy approach is applied to compute the stress‐strain response. This indicates the importance of modeling the SMA wire‐matrix interface effect, and in particular, the energy exchange between the constituent phases. The results have been compared for different geometric parameters as well as volume fractions of the constituent phases under different loading conditions.

Pattern Sensitive Placement Perturbation for Manufacturability

The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers. The quality and robustness of lithography directly depend on layout patterns. It becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, three algorithms, namely, cell flipping algorithm, single row optimization approach and multiple row optimization approach, are proposed to tune any existing cell placement to be lithography friendly. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between critical dimension (CD) variation reduction and wirelength increase. Using lithography simulations, our experimental results demonstrate that over 15% CD variation reduction can be obtained in post-OPC stage by the new approaches while only less than 1% additional wire is introduced.

Multivoltage Floorplan Design

Energy efficiency has become a very important issue to be addressed in today's system-on-a-chip (SoC) designs. One way to lower power consumption is to reduce the supply voltage. Multisupply voltage (MSV) is thus introduced to provide flexibility in controlling the power and performance tradeoff. In region-based MSV, circuits are partitioned into ?voltage islands? where each island occupies a contiguous physical space and operates at one voltage level. These tasks of island partitioning and voltage level assignment should be done simultaneously in the floorplanning process in order to take those important physical information into consideration. In this paper, we consider this core-based voltage island driven floorplanning problem including islands with power down mode, and propose a method to solve it. Given a candidate floorplan solution represented by a normalized Polish expression, we are able to obtain optimal voltage assignment and island partitioning (including islands with power down mode) simultaneously to minimize the total power consumption. Simulated annealing is used as the basic searching engine. By using this approach, we can achieve significant power saving (up to 50%) for all datasets, without any significant increase in area and wire length. We compared our approach with the most updated previous work on the same problem, and results show that our approach is much more efficient and is able to save more power in most cases. We have also studied two other approaches to solve the same problem, a simple dynamic programming approach and a lowest possible power consumption approach. Experimental results show that ours can perform the best among these three approaches. Our floorplanner can also be extended to minimize the number of level shifters, to address a minVdd version of the problem and to simplify the power routing step by placing islands close to their corresponding power pins.

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS

Power-gating has been widely used to reduce subthreshold leakage current. However, the extent of leakage saving through power-gating diminishes with technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-gating involves substantial increase of area and wirelength. A circuit technique called supply switching with ground collapse (SSGC) has recently been proposed to overcome the limitation of power-gating. The circuit technique is successfully applied to the register file of ARM9 microprocessor in a 1.2 V, 65-nm CMOS process, and the measured result is reported for the first time. The leakage current is reduced by a factor of 960 on average of 83 dies at 25°C , and by a factor of 150 at 85°C. Compared to a register file implemented in conventional power-gating, leakage current is cut by a factor of 2.2, demonstrating that SSGC can be a substitute for power-gating in nanometer CMOS.