Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs

Abstract

In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in gate-level monolithic 3-D (M3-D) ICs across different technology nodes. Our studies show that PDN worsens routing congestion more severely in M3-D ICs than in 2-D designs due to the significant reduction in resources for 3-D connections. The relative impact worsens at advanced technology nodes due to higher congestion of interconnects. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues further in 3-D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in M3-D ICs than through silicon via-based 3-D and 2-D designs because of the higher integration density and the severe competition between signal and power connections. We also compare the impact of PDN on full chip routing in M3-D ICs versus face-to-face 3-D ICs. Lastly, we use various PDN design optimization techniques for M3-D ICs at different nodes and obtain up to 13.9% signal wirelength and 17.6% total power reduction under the given IR drop budget.