Wirebond Package Research Articles

Integrated lithium niobate Vernier micro-ring filter with wide and fast tuning capabilities

Tunable optical micro-ring filters play significant roles in optical communications, microwave photonics, and photonic neural networks. Typical micro-ring filters are based on either a thermo-optic (TO) effect with microsecond timescales or an electro-optic (EO) effect with a limited tuning range. Here, we report a continuously tunable lithium niobate on insulator (LNOI) Vernier cascaded micro-ring filter with wire-bonded packaging integrated with both TO and EO tuning electrodes, featuring a 40-nm free spectral range (FSR), 2.3 GHz EO bandwidth, and a high sidelobe suppression ratio of 21.7 dB, simultaneously. Our high-performance optical micro-ring filter could become an important element in future LNOI photonic circuits with applications in high-capacity wavelength-division multiplexing (WDM) systems, broadband microwave photonics, fast-tunable external-cavity lasers, and high-speed photonic neural networks.

Glass Panel Embedding (GPE) for High-Frequency Applications

Embedded Wafer Level Fan Out (WLFO) packages have disrupted the entire semiconductor industry due to its benefits in size, cost, electrical and thermal performance, reliability and potential for heterogeneous integration when compared to traditional flip- chip and wire bond packages. Although it was initially designed to extend package I/O counts beyond fan-in Wafer Level Packages (WLP), the scope of WLFO technology has expanded significantly in recent years to include multi-die SiP modules with high-density RDL, as well as high I/O logic and memory integration. Most WLFO packaging technologies today use epoxy-based mold compounds as the carrier [1]. 3D integration in WFLO, today, is primarily pursued by means of a Through Encapsulant Via (TEV) which is a vertical interconnect through the mold compound in the fan-out area. However, the use of mold compounds limits the scope of current WLFP packages in a number of ways: (i) mold compounds have a huge CTE mismatch with silicon affecting reliability (ii) It is difficult to populate high-density fine RDL on mold compounds and also achieve good layer to layer registration (iii) mold compounds suffer from large area warpage that hinder panel-scale processing which may reduce cost by up to 2-4x, depending on the package and panel sizes, the number of die per package, and the number of RDL layers. In order to address these limitations, Georgia Tech has been developing the key technologies necessary for Glass based panel fan-out technology. Glass, when used as a substrate for die embedding, not only outperforms other organic solutions, but also provides many other benefits not found in existing WLFO technologies. The smooth surface (<5 nm) and high-dimensional stability (~1 um panel registration) of glass enables high-density silicon-like RDL wiring and BEOL-like I/Os even on large panels, thus increasing productivity and lowering cost, bringing an unparalleled combination of high I/Os and low cost. The CTE of glass can be tailored between 3 and 11 ppm/K, thus, improving reliability and enabling the direct surface mounting onto the board unlike some high-density fan-out packages that require an organic package to connect to the board for large body sizes. Glass also excellent moisture resistance that becomes an important consideration over mold compounds. Glass fanout packages can be fabricated either with or without a carrier. In the first case, cavities are formed in glass and dies are placed inside them. Following this, polymer RDL layers are built on either side of the substrate and interconnected through Through-Glass-Vias (TGVs) [2]. In the second case, through cavities are cut on a glass panel with TGVs and mounted on to a 1mm-thick glass carrier [3]. Dies are placed in the cavities and epoxy polymers are laminated on either side using a double carrier process following with RDL metal layers are built using a semi-additive process. Both these processes have their advantages and disadvantages in terms of ease of manufacturability, thermal limits and also package thickness. In this paper, we discuss in the detail the advantages and limits of these process flows and provide design guidelines for panel scalability from warpage modeling. The electrical performance of both these package structures are also compared considering an ultra-thin packaging topology and low-loss RF chain interconnected from a chip to antenna array, which consists of transmission lines, through-package vias, and microvias. Conductor-backed co-planar waveguides and striplines are formed in high-density interconnect layers with low-loss (Df=0.0025 @ 28GHz) dielectric build-up thin films. Through-glass vias and microvias are employed for vertical interconnects in the proposed packaging architecture. In summary, this paper presents the different process technology options for glass-based panel fanout packaging addressing electrical and thermal performance and panel scalability through warpage modeling. The paper also presents design guidelines for Glass fanout packages for high-frequency applications.

FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch

The impact of the pandemic on the semiconductor and electronics packaging supply chains has been in the news for over a year now. Current projections suggest the supply chain crunch could impact various industries through 2022 and 2023. While there are many ramifications of this shortage, one is certainly the impact on cost. Pricing for packages built with more mature technologies, such as wire bond and flip chip, has changed dramatically. Both of these mature technologies have typically been seen as lower cost options than newer technologies, such as fan-out wafer level packaging (FOWLP). Due to the recent shortages, the cost comparison is no longer as straight-forward as it was before. This paper will analyze the cost of building various packages using flip chip, wire bond, and FOWLP technologies. Factory overhead, indirect costs, and profit margins will be taken into account to turn this into a price comparison, rather than just a comparison of direct costs. The analyses will include the price of a package built using FOWLP technology, the price of flip chip and wire bond packages built before recent supply chain disruptions, and the new expected prices of flip chip and wire bond packages. Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is to understand how supply chain disruptions have changed the cost parity points of wire bond, flip chip, and FOWLP packages.

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design

With the rapidly growing demand for system-level integration, package substrates have become one of the most important carriers in semiconductor industry. Fine pitch ball grid array (FBGA) packaging is a widely used technology thanks to its relative cost-effectiveness compared to other advanced packaging technologies. In addition, it is also widely used in space-constrained applications, such as mobile and handheld devices. These packaging substrate interconnections are usually customized by layout engineers taking many complex and stringent design rules into consideration. However, fully net-by-net manual design for FBGA is time-consuming and error-prone. In this article, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-dependent constraints but also take the problem of mismatched via dimension into account, which is caused by the mechanical processes and greatly increases design complexity. In addition to the ILP formulation for substrate routing, three optimization stages and several ILP constraint reduction techniques are also developed to boost the run time of ILP solver. Experimental results indicate that the proposed framework can achieve high routing completion rates, which could effectively reduce the cycle time of substrate layout design. In addition, in combination with the proposed optimization strategies, 278× speedup can be achieved compared to the ILP constraint optimized router.

On the Design of Broadband Truly Balanced Inductor-Less Differential-to-Single-Ended Converter in CMOS Friendly to Wire-Bond Package

This brief presents a broadband inductor-less differential to single-ended (D2S) converter employing complementary structure with series resistor. The developed D2S converter has a unique advantage in terms of amplitude and phase balance performance, achieving true balance in theory and while maintaining wire-bond package friendliness. The D2S converter is validated in a prototype of broadband driver amplifier (DA) for the transmitter front-end and fabricated in 65 nm CMOS process. The measurement results show an amplitude and phase error of less than 0.2 dB and 1∘, respectively, over a frequency range of 0.1 to 6 GHz. The proposed D2S occupies a core chip area of only 0.04×0.1 mm and consumes 6.5–7.4 mW power from a 1.2 V supply voltage.

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{8}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{0}.\text{75}$</tex-math> </inline-formula> mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain–source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C/W; and 3) after 2000 thermal cycling cycles, drain–source ON-state resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{DS\text{(}\text{on}\text{)}}}$</tex-math> </inline-formula> increased by less than 2%, which revealed the higher reliability of the package under thermal cycling.

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS high granularity timing detector

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 °C shows negligible degradation over 16 days.

Differential Wideband Antenna on Organic Substrate at 240 GHz with a Differential Wirebond Package

Differential Wideband Antenna on Organic Substrate at 240 GHz with a Differential Wirebond Package

Design and Optimization of Gate Driver Integrated Multichip 3-D GaN Power Module

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are excellent power semiconductor devices due to their superior material properties compared to their silicon (Si) counterparts. It has demonstrated a fast switching speed with high dV/dt, enabling the designer to push the switching frequency toward the MHz range. However, traditional wire-bonded packaging becomes a limiting factor in fully harnessing the benefits offered by these advanced power devices, as it is likely to introduce voltage overshoot, oscillation, parasitic turn-on, and electromagnetic interference (EMI) issues; thus, improved and advanced packaging structures are a must to bridge the gap. Besides, the unique electrical behavior and footprint of GaN compared to Si and Si carbide make them have different requirements for power module integration. To seek a viable solution, a globally optimized double-sided cooled, gate driver integrated 650-V/60-A GaN half-bridge power module is presented herein. The proposed 3-D integrated hybrid solution delivers an optimized package, having power loop inductance and thermal resistance as low as 0.91 nH and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.38~^{\circ }\text{C}$ </tex-math></inline-formula> /W, respectively, which is verified using simulation and experimental results. The overall utility of the design improved proportionately by introducing simple, yet effective electrical/thermal codesign approaches, which can be applied to future power modules, designed for separate applications.

(Invited) 75 kVA 1kV DC 50 kHz Air-Cooled Inverter with 1.7 Kv SiC Mosfet and 3D-Printed Novel Modular Packaging Structure

In recent years, some air-cooled inverters have been developed and demonstrated for grid applications using SiC power modules. All of these SiC power modules utilize the conventional single-side wire-bonding packaging structure, i.e. only one side of the power module is attached to heat sinks. The potential of silicon carbide (SiC) devices, such as high power density, high frequency and high temperature operation, have not been fully explored yet. To deal with this issue, several research efforts have focused on the development of SiC power modules with double sided-cooling capability, utilizing planar packaging structure . These power modules are able to achieve a comprehensive improvement in overall volume / size, parasitic parameters, as well as thermal impedance. However, some key aspects limit the real application of planar packaging structures. One main reason is that double-side solderable SiC devices are generally not commercially available. Other challenges include interconnection alignment issue, limited choices for die-attach material, complicated fabrication process, etc With the goal of exploring SiC device potential without complicated packaging, an all-SiC air-cooled wire-bonding power module and inverter is developed for grid applications based on 3D printing technology enabling: new packaging structure, optimized heat sink, and more-compact system integration.This paper presents the design and development of an 75 kVA, 50 kHz, 1kV air-cooled Silicon Carbide inverter using advance packaging and additive manufacturing technology. Specifically, an air-cooled power module with a new packaging structure is design, aiming at reduced thermal resistance for high temperature and high-power density operation. The detailed research work involves the design of a new packaging structure, wire-bond SiC power module design and fabrication, as well as associated power stage and control circuit design. The total volume of the power module for the prototype is 99725 mm3 a 48% volume reduction volume compared to previous work reported by the authors. The air-cooled module assembly incorporates three major parts: SiC MOSFET phase leg module with split high side and low side switches, a gate driver with cross-talk and short circuit protection functions, and 3D printed module package. In addition , the thermal performance of the inverter is also evaluated and the results show the maximum junction temperature of the bare die is 103C. Based on the air cool module, a 50-kW three phase inverter is developed and tested to further verify the superior thermal performance of the proposed packaging structure. The experimental results show that the peak efficiency is 99.1% at 1kV,50 KHz switching and 50 kW operating condition. Figure 1

Hierarchical Attention-Based Machine Learning Model for Radiation Prediction of WB-BGA Package

Rapid increase in operating frequency of integrated chips and intricacy of electronic packages outpaces the ability of conventional methods in coping with the growing complexity of electromagnetic interference (EMI) issues. To address it, several machine learning (ML) methods––deep neural network (DNN), convolutional neural network, support vector regression, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> -nearest neighbor, and linear regression are constructed to acquire the best ML model to accurately and rapidly predict the maximum 3-m radiated electric field of a wire-bond ball grid array package. The key hyperparameters of different ML models are tuned respectively to attain the least prediction error for each model. Among the optimized ML models, the prediction accuracy of the DNN model is the highest. In this article, a hierarchical attention-based DNN model is proposed and discussed in depth to reduce the number of training datasets, and identify the structural parameters with large contributions to radiation prediction. These structural parameters with contributions can guide the packaging design. The DNN model with attention-weight input requires fewer training datasets than the original DNN model. Furthermore, the experimental measurement for EMI radiation of a test package board is implemented, and the far-field results show the effectiveness and feasibility of the DNN model.

Vertically Stacked, Flip-Chip Wide Bandgap MOSFET Co-Optimized for Reliability and Switching Performance

Silicon carbide (SiC) wide-bandgap semiconductors (WBGs) offer a significant improvement in high voltage and high-temperature stability; however, their associated packaging often can impede electrical performance and reliability. In this study, a new flip-chip package, implementing a vertically oriented metal oxide semiconductor field effect transistor (MOSFET) was investigated to achieve co-optimized thermomechanical reliability with low parasitic inductance. The architecture improves upon wire-bonded packages by allowing for top-side cooling and reduced power loop inductance. Herein, the design effects of solder material and diameter as well as pitch size and drain connector geometry on thermal cycling reliability of the device were investigated using finite-element methods. Additionally, thermal resistance in association with a parasitic inductance of varying drain connector architectures is compared while utilizing symmetry to facilitate manufacturability. By considering the complex effects of geometry and material, the optimal architecture was selected and fabricated. When comparing to a prior flip-chip design effort, this simulation-based design optimization was able to improve the solder fatigue life up to 11 times while reducing parasitic inductance by 30 times. Experimentally, the associated electrical performance of the novel device showed improved switching behavior in double-pulse testing of a half-bridge module, with nearly negligible overshoot voltage on switching, where an equivalent discrete package exhibited ~100% overshoot and ~24% inductance improvement at the module level.

Review of Packaging Schemes for Power Module

SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

Corrosion-induced degradation and its mechanism study of Cu–Al interface for Cu-wire bonding under HAST conditions

This study explores the Cu wire corrosion-related issues and provides solutions for evaluation & analysis as the Automotive Electronics Council (AEC) continually formulates industry specification and qualification procedures for evolving Cu wire-bonding technology. Evaluation of molding resin attributes concerning about the preferential Intermetallic Compounds (IMCs) corrosion and formation of oxidation layer in the Cu–Al interface during accelerated reliability stress test (bias HAST) is discussed. Failure mechanism for Cu–Al system is microgalvanic corrosion accompanied with crevice/pitting corrosion-induced deterioration in the presence of moisture and ion impurity from resin encapsulatants. Failure analysis techniques conduct on corrosion-induced broken stitch bond issue are proposed and root cause is identified. Electrochemical studies of Au, Cu, Pd-doped Cu (PCC) and Ag alloy wire presents here for further understanding the corrosion behavior in wire-bonding packages. Potentiodynamic polarization is used to investigate the electrolyte property and corrosion performance of these specimen in the corrosive medium. The results provide vital information on the Cu corrosion study not only in ball bonds but also in stitch bonds which are of practical value to the current industry under “design for reliability” (DfR) approach to product development.

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

The local stress distribution in a silicon chip encapsulated in an area-arrayed copper pillar-type flip-chip package was evaluated using specially designed test chips. Stress is sensed using piezoelectric resistors, which are p-type and n-type diffusion resistors embedded in a silicon chip measuring 7.8 mm $\times7.8$ mm. Each piezoelectric resistor measures approximately 0.03 mm in length and 0.002 mm in width, which is sufficiently small to measure the local stress distribution near each copper pillar. As a result of this study, it is revealed that the copper pillars have an impact on the local stress distribution in silicon chips, in particular producing a large stress gradient near the copper pillar edge, compared to the conventional wire-bonded packages. Since large stress gradients disturb pair characteristics of analog circuits, in order to design a high-precision integrated circuit employing a copper pillar-type flip-chip package, a specific regulation method to avoid overlap with the copper pillars is needed to maintain the accuracy of the analog circuits.

Thermal Optimization and Characterization of SiC-Based High Power Electronics Packages With Advanced Thermal Design

A single-phase high power electronics package is designed and developed in this paper. The developed power package achieves a significant thermal performance improvement compared with the conventional wire-bonded power package. The improvement is attributed to two features of the package design. First, the SiC chips are embedded into the active metal brazed (AMB) substrates with specially designed cavities, as such the heat transfer path from the embedded SiC chips to the liquid-cooled heat sink attached to the bottom side of the AMB substrate is shortened. Hence, the thermal performance of the package is improved. Moreover, customized copper clips are introduced as the electrical interconnections between the SiC chips and the top metal layer of the substrate at the same level, and the top surface of the power package remain flat. As such another heat sink can be added to the top side of the package to further improve the thermal performance of the power package through the double-side cooling (DSC) scheme. The simulation results show that the junction-to-case thermal resistance (Theta JC) of the optimized power package is about 50% less than the Theta JC of the conventional wire-bonded power package with the same package size and the same power rate. Further applying the DSC scheme to the proposed power package, which is not suitable to the conventional wire-bonded power package, the Theta JC of the proposed power package reduces another 20%. In addition, the effects of the core layer (i.e., material and thickness) and the metal layer (i.e., materials and thicknesses) of the AMB substrate, as well as the die attach (i.e., material and thickness) on the Theta JC of the proposed power package are investigated systematically. As such the thermal performance of the power inverter package is further elaborated. Finally, the thermally enhanced power package is fabricated and assembled. Thermal characterization has been conducted, and the thermal performance of the developed power package has been evaluated. The simulation results and characterization results match well with each other.

Comparative Study of Chloride and Fluoride Induced Al Pad Corrosion in Wire Bonded Packaging Assembly

Microelectronics are used in virtually all electronic equipment’s nowadays ranging from medical instruments, automobiles, computers, cell phones and home appliances. Wirebonding process which connects the chip to the lead frame in IC packaging plays a very important role in the commercial production of IC’s. Chip usually consists of Al bond pads with Cu/Au wires. Thin film Al bond pads are easily vulnerable to corrosion in presence of contaminants and moisture. Bond pad corrosion is one of the common modes of corrosion failure in wire-bonded devices IC packaging. Improper rinsing, packaging and passivation defects allows moisture and contaminants into bondpads resulting in severe corrosion. Most common source of this corrosion comes from the presence of halide ions contamination as (Cl-, F-, Br- etc.) However, the corrosion morphology and the severity varies from different ions contamination as the chemistry governing the corrosion differs from one ion to another. Our research is focused on key findings on corrosion of Aluminum bond pad due to chloride (Cl-) and fluoride (F-) contamination. Our central motivation is to identify this F- corrosion mechanism, so that it will help to develop a strategy to prevent it and study the comparison between Cl- and F- Corrosion using Micro-pattern corrosion screening technique, Wire-bonded device (WBD) and other characterization technique such as GC-MS, SEM and tafel. GC-MS reveals that H2 gas evolution is observed during Cl- corrosion of the WBD, whereas little or no H2 evolution is observed during F- corrosion. SEM and EDX reveals no presence of Cl- in the corroded areas of its corrosion, whereas strong F- signal is observed in F- corrosion of the bondpads revealing, that the corrosion products formed on the surface has very poor solubility showing that Cl- and F- has a complete different corrosion morphology. Striking contrasts in corrosion morphology observed during the Cl- and F- corrosion were explained in the present work and will lead to better understanding of factors influencing the bond pad corrosion leading to the wire bond failure in IC packaging devices. [Fig. 1] Figure 1

Electromagnetic and Thermal Characteristics of Graphite for Radiation Suppression in Wire-Bonded Package Heat Sink

Heat sink is widely mounted on the integrated circuits to optimize thermal performance. Unfortunately, the cavity resonance between heat sink and package substrate could lead to severe radiation problem, causing that the product fail to satisfy the relevant electromagnetic interference (EMI) standards. It is a critical challenge to simultaneously obtain the excellent radiation attenuation and desirable thermal performance. In order to solve the problem, a combination of ring-shaped absorbing material and flat-shaped graphite is proposed in this paper. Based on a typical wire-bonded package, the effect of graphite on mitigating radiation and optimizing the thermal performance is investigated. As the graphite size varies from 20 to 45 mm, temperature reduction 5 °C and radiation attenuation 10 dB absorption bandwidth is realized. The experiment for EMI radiation is conducted in a semianechoic chamber, and the results of simulation and experiment matched well.

Advanced Packaging for Automotive Dashboard Application

Abstract The current automotive market for the integrated circuit (IC) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced packages for next generation automotive market requirements. Automotive IC's are traditionally wirebond packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards high performance flip chip packages for automotive infotainment, GPS, and radar applications. In this study, a comprehensive view of the evolving packaging landscape from traditional wirebond to flip chip interconnect to advanced fan-out wafer level packages will be discussed. The pros and cons of each packaging technology will be examined. Packaging roadmap details will be discussed along with assembly process information, determining the right bill of materials (BOM), and extensive package and board level reliability (BLR) including grade 1 and grade 0 reliability data will be discussed.