Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

Abstract

The local stress distribution in a silicon chip encapsulated in an area-arrayed copper pillar-type flip-chip package was evaluated using specially designed test chips. Stress is sensed using piezoelectric resistors, which are p-type and n-type diffusion resistors embedded in a silicon chip measuring 7.8 mm $\times7.8$ mm. Each piezoelectric resistor measures approximately 0.03 mm in length and 0.002 mm in width, which is sufficiently small to measure the local stress distribution near each copper pillar. As a result of this study, it is revealed that the copper pillars have an impact on the local stress distribution in silicon chips, in particular producing a large stress gradient near the copper pillar edge, compared to the conventional wire-bonded packages. Since large stress gradients disturb pair characteristics of analog circuits, in order to design a high-precision integrated circuit employing a copper pillar-type flip-chip package, a specific regulation method to avoid overlap with the copper pillars is needed to maintain the accuracy of the analog circuits.