Wide Load Current Range Research Articles

A high-efficiency and wide-load current range LDO with dynamic loop gain control technique

The design proposes a low-dropout regulator incorporating dynamic loop gain control to accommodate a wide load current range. It introduces a multi-phase error detection mechanism, a tri-state damping selector, and a dynamic integration shift register. These elements predict load variations and dynamically increase loop gain when the load variation is significant, all without increasing the input clock. This approach achieves a fast response and low power consumption simultaneously. The chip was implemented in 0.18 μm CMOS, with an input operating voltage of 1.2 V and an output voltage of 1 V. The measured results revealed that it could provide output currents from 0.5 to 150 mA, indicating that it had a 300 times wider current range. The maximum current efficiency was 99.93%, and the core area was 0.198 mm2.

High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

AbstractThis work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current ( ) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of , respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full of 50 mA.

Hybrid Modulated DCDC Boost Converter for Wearable Devices

Wearable devices require power management systems to achieve high conversion efficiency over a wide range of load currents. Multi-mode mixed modulation can be used in DCDC converters to achieve high efficiency over a wide load current range. The DCDC boost converter proposed in this paper uses a hybrid modulation of DGM (Deep Green Control Mode), PCMC (Peak current mode control)-PFM (Pulse Frequency Modulation) and PCMC-PWM (Pulse Width Modulation). The converter switches smoothly from PCMC-PFM to PCMC-PWM mode under load-current-based conditions and without any mode selection module. The proposed DCDC boost converter is fabricated in a 0.18 μm CMOS process with a Die area of 1.24 × 0.78 μm2. The input voltage range is 0.8–5 V, the output voltage is 5 V, and the load current range is 5–300 mA. Experimental results show that the boost converter can achieve 94.7% peak efficiency. Efficiency of more than 90% can be achieved in the load current range of 30–300 mA.

An area-efficient automotive LDO with scalable maximum load current exhibits excellent response to line and load transients

A compact LDO with scalable maximum load current is presented. A transconductor with multiple current outputs implements the error amplifier, as well as two feed-forward paths. A push-pull output stage is employed to drive the gate of the pass transistor. Zeros are created by the feed-forward paths, as well as by an RC network to realize an area- and power-effective frequency compensation, that ensures the LDO stability over a wide range of load currents and capacitances. The proposed LDO was implemented in a 0.13 µm CMOS process. The sizing strategy is presented in the paper, along with simulation and measurement results that validate the design. The LDO provides a stable 1 V output voltage when the input voltage varies between 1.2 V and 1.5 V, the load current varies between zero and 100 mA, and the load capacitance takes values between 100 nF and 10 µF. Its nominal quiescent current is just 9.6 µA while the die area is exceptionally small, only 0.0065 mm2. The integrated LDO exhibits excellent responses to load and line transients: when the load current jumps between 100 µA and 100 mA in 0.3 µs the measured output voltage overshoot and undershoot are below 3.6% of nominal value for CLOAD = 470 nF; the measured overshoot and undershoot caused by the line voltage jumping between 1.3 V and 1.5 V in 3 µs are smaller than 1.2% for the same CLOAD.

Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> = 0 and under 60 mV for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ </tex-math></inline-formula> , when the load current varies between 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and 100 mA in 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> . The LDO requires only 6.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current and occupies 0.018 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area.

Energy and noise characteristics of a SEPIC buck-boost converter with unipolar and bipolar output

Some advantages of the SEPIC buck-boost converter makes it stand out from other configurations. It makes possible to obtain from a unipolar input voltage both unipolar and bipolar output voltage with a good symmetry between positive and negative output voltages. It also provides efficient performance as well as circuit simplicity in unipolar and bipolar topology owing to the use of a single switch which can be operated by available integrated controllers of boost converters. The article considers the topologies of a SEPIC buck-boost converter built according to the traditional scheme (with two inductors) and according to the scheme on magnetically coupled chokes. To analyze the processes and factors affecting the converter operation efficiency, a circuit simulation has been done using the Electronics Workbench. The results of the investigation of a pulsed DC converter of input voltage to unipolar or bipolar output voltage using SEPIC buck-boost topology are presented. The circuit simulation enables to specify the switching process characteristics, to estimate the ripple level of the input current and its spectral characteristics, and to develop recommendations concerning the choice of parameters of converters elements and generation of control signals. Based on the simulation results, the load, control, and noise characteristics of the converter are obtained. The level of symmetry of positive and negative output voltage is investigated for the converter on discrete and magnetically coupled chokes. The assessment of the effect of leakage inductance on converters with magnetic coupling of inductive elements is given. Examples of practical implementation of converters built according to the SEPIC topology are shown. It is found that the resistance of the choke windings, which is less than 0.5 Ohm, has practically no effect on the efficiency of the converter, retaining the factor of about 0.9 in a wide range of load currents, while the main source of conversion losses is a passive diode switch. Synchronous converter circuits of a number of manufacturers are more efficient, but require more complex controllers for active switches with elements for protection against through currents.

A transient enhanced cap-less low-dropout regulator for wide range of load currents and capacitances

In this paper, a transient enhanced flipped voltage follower (FVF) based cap-less low-dropout (LDO) regulator for wide range of load currents and capacitances is presented. The proposed LDO uses a slow–fast loop architecture with three feed-forward paths to enhance the transient behaviour and to stabilize the feedback loop. These feed-forward paths help to eliminate the minimum load current and load capacitance constraints with improved transient responses. A simple damping-ratio enhancer (DRE) is used to stabilize the loop further. This LDO provides the regulated power supply voltage of 1 V with good load and line regulations. It achieves the settling time of 200 ns with the minimum edge time of 100 ps for the load currents from 0 to 50 mA and the load capacitance ranges from 0 to 2 nF. The proposed LDO is implemented in 130 nm CMOS technology and consumes only a quiescent current of 95 μA.

An Adaptively Biased Output-Capacitor-Free Low-Dropout Regulator With Supply Ripple Subtraction and Pole-Tracking-Compensation

This article presents an adaptively biased output-capacitor-free low-dropout regulator that achieves high power supply rejection for wearable biomedical system-on-chips (SoCs). Adaptive biasing is implemented to achieve both fast transient responses and high power conversion efficiency, and the common-gate current feedback loop enhances the dc gain of the error amplifier by 10 dB. The proposed supply ripple subtraction reference buffer constitutes a reversed-phase power supply rejection (PSR) path that counteracts the increase in the output voltage due to the in-phase PSR path, and PSR is enhanced significantly in the range of 1 MHz. The proposed pole-tracking-compensation maintains sufficient phase margin over a wide load current range. Designed and fabricated in a 0.18 μm CMOS process, the prototype silicon area is only 0.0113 mm $^2$. The total quiescent current is 8.6 μA at no load current, and the maximum current efficiency is 98.8$\%$ at full load current of 20 mA.

Distributed thermal monitoring of lithium ion batteries with optical fibre sensors

Real-time temperature monitoring of li-ion batteries is widely regarded within the both the academic literature and by the industrial community as being a fundamental requirement for the reliable and safe operation of battery systems. This is particularly evident for larger format pouch cells employed in many automotive or grid storage applications. Traditional methods of temperature measurement, such as the inclusion of individual sensors mounted at discrete locations on the surface of the cell may yield incomplete information. In this study, a novel Rayleigh scattering based optical fibre sensing technology is proposed and demonstrated to deliver a distributed, real-time and accurate measure of temperature that is suitable for use with Li-ion pouch cells. The thermal behaviour of an A5-size pouch cell is experimentally investigated over a wide range of ambient temperatures and electrical load currents, during both charge and discharge. A distributed fibre optical sensor (DFOS) is used to measure both the in-plane temperature difference across the cell surface and the movement of the hottest region of the cell during operation, where temperature difference is the difference of temperature amongst different measuring points. Significantly, the DFOS results highlight that the maximum in-plane temperature difference was found to be up to 307% higher than that measured using traditional a thermocouple approach.

A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS

This article proposes a digitally assisted analog low-dropout (DA-ALDO) regulator, a hybrid solution which realizes tight regulation, wide load current range, area-efficient power transistor utilization, and fast transient speed in the meantime. The DA-ALDO employs an analog control scheme in steady state. Consequently, an accurate output voltage is available with a high-gain amplifier and no limit cycle oscillation occurs. A digital control scheme is invoked only upon transient events for speed enhancement, quiescent current reduction, and switching noise suppression. The digital controller adopts a hybrid algorithm of binary and multiple-unary schemes for an optimized tradeoff between voltage accuracy and settling time. The proposed DA-ALDO is fabricated in a 65-nm CMOS process with a maximum load current of 500 mA and a 250 pF on-chip output capacitor. Operating with an input of 1.2 V and outputs of 0.6-1.0 V and delivering from 500 μA to 500 mA (or a 463× load current range with a current efficiency η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> > 90%), the DA-ALDO achieves 30-μV/mA load regulation while consuming 120-μA quiescent current. The measured undershoot/overshoot and the corresponding settling time with a 450-mA/100-ns load current step are 55 mV and 174 ns and 56 mV and 220 ns, respectively. The figure of merit (FoM) is as low as 0.0073 ps.

Triple-Mode Switched-Inductor-Capacitor DC-DC Buck Converter with Reusable Flying Capacitor and Bang-Bang Zero-Current Detector for Wide Load Current Range

Although the capacity of a battery with a small form factor is extremely low, demand for long usage time of Internet of Things (IoT) products is increasing. Owing to this limitation of the battery, power management integrated circuits (PMICs) are used for extending the battery usage time with high efficiency. In particular, since IoT devices are mostly in the sleep mode in the idle state, PMICs should achieve high efficiency for ultralight loads in the sleep mode as well as for heavy loads in the active mode. In this paper, an accurate bang-bang zero-current detector (to prevent a reverse inductor current) and a triple-mode switched inductor-capacitor dc-dc buck converter with a reusable flying capacitor are presented; these techniques can maintain high efficiency over a wide load current range. The proposed buck converter was fabricated in a 0.18-μm 1P4M CMOS process. A power conversion efficiency exceeding 85% was achieved in the load range of 100 µA to 300 mA.

Fixed air flow-rate selection by considering the self-regulating function of low power air-cooled PEMFC stack

In this study, it is found that the air-cooled proton exchange membrane fuel cell (PEMFC) has a self-regulating function in terms of its thermal and water balances within the fuel cell. Such a function enables the fuel cell's operation to be stable and efficient without any electronic controlling circuit to control the operating parameters. A small air-cooled PEMFC stack (15 cells with a rate power of 60 W) integrated with an axial fan is used for this experimental study to verify the self-regulating feature. The results show that the air-cooled open-cathode PEMFC stack can run stably and efficiently under a wide range of load currents at a fixed air flow rate. The best fuel cell performance and maximum system net power output are achieved at an air flow of 55.7 SLPM. To further validate the results, the temperature distribution and cell voltage distribution of the stack are simultaneously measured under different loads. The results demonstrate that the temperature and cell voltage of the stack are evenly distributed at the air flow of 55.7 SLPM. The present study may provide guidance in the design of a cooling subsystem of a small and compact fuel cell system incorporating an air-cooled open-cathode PEMFC.

Adaptive‐biased sense‐FET–based inductor‐current sensor for 10‐MHz buck converter

SummaryA sense field effect transistor (FET)–based inductor‐current sensor for buck converters is introduced in this paper. The proposed current sensor adopts and realizes piecewise‐linear adaptive bias to maintain consistent bandwidth and phase margin in the sensor's control loop throughout a wide range of load currents. Moreover, the specially designed turn‐on/off process of switches is introduced together with the sole gain–boosted amplifier to avoid the sharp transitions in the sensed peak and valley currents during the deadtime zone of synchronous buck converters. Simulation results of the proposed sensor show an 11.6‐dB rise in direct current (DC) gain at light load (approximately 200 mA) and 21° improvement in phase margin at heavy load (approximately 2 A), compared with the traditional structure with fixed‐bias current. Furthermore, the variation in the unity gain bandwidth of the proposed structure across the whole load range is 12.8 times lower than that of the traditional designs.

An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Traditional digital systems employ independent loops to control supply voltage ( ${\mathit {V}}_{\text {dd}}$ ) and clock frequency ( $f_{\text {clk}}$ ). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the system clock to a reference clock (REFCLK). Concurrently, a voltage regulation loop sets ${\mathit {V}}_{\text {dd}}$ to a target value under rapidly varying load current or line-side disturbances. Limitations in voltage regulator loop bandwidth result in significant ${\mathit {V}}_{\text {dd}}$ fluctuation, leading to timing slack degradation in digital voltage domains. Maintaining timing slack in the presence of supply noise or temperature (T) variation incurs energy-wasteful ${\mathit {V}}_{\text {dd}}$ guardbands. In this article, we present a unified clock and power (UniCaP) architecture that instantaneously adapts $f_{\text {clk}}$ to ${\mathit {V}}_{\text {dd}}$ and $T$ variations, requiring minimal guardbands. UniCaP absorbs ${\mathit {V}}_{\text {dd}}$ control into the clock regulation loop, using it to adjust $f_{\text {clk}}$ and lock system clock to REFCLK. UniCaP enables all-digital construction with aggressive ${\mathit {V}}_{\text {dd}}$ guardband reduction and the capability for on-the-fly dynamic voltage and frequency scaling (DVFS) events. We deployed the UniCaP architecture on a 65-nm buck converter test chip powering a 0.6–1.0-V Cortex-M0 microprocessor with autonomous transition between continuous and discontinuous conduction modes (CCM/DCM) in order to support a wide load current range. The UniCaP test chip demonstrates 82% average ${\mathit {V}}_{\text {dd}}$ guardband reduction, without any performance loss from adaptive clocking, and temperature margin reductions of 40–55 mV.

A Current-Mode Delay-Based Hysteretic Buck Regulator With Enhanced Efficiency at Ultra-Light Loads for Low-Power Microcontrollers

A current-mode buck regulator with delay-based hysteretic control for microcontroller applications is proposed. Unlike conventional hysteretic buck regulators with accurate explicit hysteretic bands, the proposed design relies only on the inherent delay of a low-speed single-threshold comparator to realize the hysteretic band, and can be seamlessly used across all loads in continuous conduction mode and discontinuous conduction mode without modifying the controller's parameters. Moreover, without additional adaptation circuits or frequency regulation loops, the proposed delay-based hysteretic operation does not increase variations in the switching frequency with process and temperature, and results in even less variations in the switching frequency with the input and output voltages when compared to corresponding designs with accurate explicit hysteretic bands. The simplicity of the design reduces silicon area and quiescent current significantly, which in turns enables achieving high efficiency at both heavy and light load conditions as strictly required by low-power microcontrollers. The regulator is designed in a 65 nm digital CMOS technology. It occupies 0.18 mm2 and supports a wide range of input voltages (1.8–4.2 V), output voltages (0.9–1.5 V), and load current (up to 300 mA). Measurement results show that the proposed regulator achieves 95% peak efficiency, while achieving between 62% and 87% efficiency at 10-μA load across all operating conditions.

A Hybrid Structure Dual-Path Step-Down Converter With 96.2% Peak Efficiency Using 250-m$\Omega$ Large-DCR Inductor

A dual-path step-down converter (DPDC) is presented for achieving high power efficiency in the mobile power management ICs (PMICs). Adopting a hybrid structure using one inductor and one flying capacitor, the proposed DPDC supplies a load current via two parallel paths, relieved an intrinsic problem of the conventional buck converter (CBC) topology, which is a significant power loss from a large DCR of the inductor ( ${R}_{\mathrm {DCR}}$ ). Therefore, DPDC achieves a high power efficiency and thus also reduces the heating problem, which is another critical issue in the mobile set. Moreover, DPDC can shrink the volume of the PMIC set with a low manufacturing cost by alleviating an ${R}_{\mathrm {DCR}}$ specification of the inductor. In this paper, although a 250 $\text{m}\Omega $ of large ${R}_{\mathrm {DCR}}$ inductor is used for our measurements, a 96.2% of peak efficiency was achieved and the power loss of total parasitic resistances can be reduced to up to 30% of that of CBC. Moreover, according to our measurement plots, it is verified that DPDC achieves the efficiency notably higher not only in a wide load current ( $I_{\mathrm {LOAD}}$ ) range but also in a wide conversion ratio ( $V_{\mathrm {OUT}}/V_{\mathrm {IN}}$ ) range, compared to CBC.

Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications

A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50[Formula: see text]mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The output voltage of the LDO was set to 1.2[Formula: see text]V for an input voltage of 1.4–2[Formula: see text]V. The Simulation results verify that the transient times are less than 2.8[Formula: see text][Formula: see text]s and the maximum undershoot and overshoot are 20[Formula: see text]mV while consuming only 26[Formula: see text][Formula: see text]A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100[Formula: see text]PF.

Fully Integrated Voltage Doubler With Dual-Mode Three-Dimensional Load Regulation for On-Chip Photovoltaic-Powered Applications

This paper presents a compact and fully integrated switched-capacitor voltage doubler for voltage boosting in photovoltaic-powered implantable devices. Gate-voltage boosting, nonoverlapping, and interleaving techniques are adopted to enhance the driving capability of the voltage doubler at low supply voltage with high efficiency. A dual-mode three-dimensional (3-D) digital control circuit is proposed to regulate the output voltage under the load current variation. The 3-D control on the number of active converter cells, operation frequency, and on -resistance enable fine output voltage regulation over a wide load current range without extensive device segmentation, thereby reducing the routing complexity and the associated parasitic losses. Other advantages are that the switching loss can be proportionally scaled with the load current for high power efficiency and the periodic charge transfer to the output can keep small for small voltage ripple. Pulse-skipping modulation is employed to allow the converter to operate under ultra-light load. The proposed voltage doubler is designed and implemented using 0.18 μ m-CMOS process. The measurement results demonstrate that the proposed converter can generate a voltage of 0.9 V from an input of 0.6 V, with a power efficiency of more than 60% within the output current range of 30–440 μ A. The peak efficiency is 73% and the active area is 0.33 mm2. These measurement results suggest that the proposed voltage doubler is suitable for voltage boosting at low voltage under the limited availability of power and area.

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.

An Adaptively Controlled 10-Output Reconfigurable Dual-Bus SIMO System With Group Allocator for Diversified Load Condition

Portable electronic devices require multiple supply voltages with relatively large differences in load currents, causing serious regulation, EMI, and efficiency problems when adopting a single-inductor multiple-output (SIMO) dc-dc converter. To resolve these issues, this paper presents a reconfigurable SIMO system with ten-output having two buses, one for heavy-load and one for light-load outputs. The converter maintains the load current condition so that each bus is well balanced even when the load currents are diversified by using the proposed group allocator, which properly assigns a bus for each output depending on its load current. Due to this load balancing function, regulation issues that could occur under diversified load conditions are resolved, and high efficiency is achieved over a wide load current range. The test chip was fabricated in 1P4M 0.18 μm CMOS process. The system has ten independently regulated outputs with an output voltage ripples below 25 mV, and greater than 81% efficiency is achieved across a wide load range (0-300 mA).