Abstract

This paper proposes a low dropout voltage regulator (LDO) that exhibits both a fast response to load transients and the ability to handle practically any load capacitor. Starting from a typical LDO topology, an error amplifier (EA) that drives a PMOS pass transistor and a passive feedback network, we inserted a novel circuit, with the input AC-coupled to the LDO output and the output connected directly to the pass transistor gate. This circuit creates an inner feedback loop able to react quicker than the main feedback loop to variations in the output voltage, and appropriately inject or sink current to/from the gate node. Moreover, the inner feedback loop helps reduce the equivalent small-signal impedance at the LDO output, which in turn reduces the impact the pole associated with the output node has on the LDO stability. A compact circuit implementation of this topology is presented in this paper: it combines the proposed fast transient & frequency compensation circuit with a high slew-rate EA. The resulting LDO was integrated in a 130 nm standard CMOS technology. The measurement results are in good agreement with simulations and validate the concept and design. The LDO provides a steady 1 V output with the supply voltage varying from 1.2 V to 1.5 V and the load current going up to 100 mA. Its fast response to load transients helps maintain the output voltage overshoot and undershoot below 250 mV for C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> = 0 and under 60 mV for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ </tex-math></inline-formula> , when the load current varies between 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and 100 mA in 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> . The LDO requires only 6.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> of quiescent current and occupies 0.018 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area.

Highlights

  • Its frequency characteristics are largely determined by two poles: the first is associated with the gate of the pass transistor, while the second is associated with the low dropout voltage regulator (LDO) output node

  • The LDO proposed in [6] uses an error amplifier (EA) based on the flipped-voltage-follower structure, with a slew rate enhancement technique for fast transient response, and a feed-forward frequency compensation network that ensures stability for CL values up to 2 nF

  • The topology of the LDO proposed in this paper is similar to the ones described above, but the local feedback is implemented by a novel circuit, which ensures both a fast response to load transients and the LDO stability for practically any load capacitance

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Summary

INTRODUCTION

The LDO proposed in [6] uses an EA based on the flipped-voltage-follower structure, with a slew rate enhancement technique for fast transient response, and a feed-forward frequency compensation network that ensures stability for CL values up to 2 nF It requires a large quiescent current, between 50 μA and 190 μA. The topology of the LDO proposed in this paper is similar to the ones described above, but the local feedback is implemented by a novel circuit, which ensures both a fast response to load transients and the LDO stability for practically any load capacitance This circuit is combined with an EA with enhanced slew-rate to obtain a compact LDO, suitable for low quiescent current operation and a small die footprint.

PROPOSED LDO
GmEA fINNER
LDO DESIGN REQUIREMENTS AND SIZING STARTEGY
CONCLUSIONS
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