A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS

Abstract

This article proposes a digitally assisted analog low-dropout (DA-ALDO) regulator, a hybrid solution which realizes tight regulation, wide load current range, area-efficient power transistor utilization, and fast transient speed in the meantime. The DA-ALDO employs an analog control scheme in steady state. Consequently, an accurate output voltage is available with a high-gain amplifier and no limit cycle oscillation occurs. A digital control scheme is invoked only upon transient events for speed enhancement, quiescent current reduction, and switching noise suppression. The digital controller adopts a hybrid algorithm of binary and multiple-unary schemes for an optimized tradeoff between voltage accuracy and settling time. The proposed DA-ALDO is fabricated in a 65-nm CMOS process with a maximum load current of 500 mA and a 250 pF on-chip output capacitor. Operating with an input of 1.2 V and outputs of 0.6-1.0 V and delivering from 500 μA to 500 mA (or a 463× load current range with a current efficiency η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> > 90%), the DA-ALDO achieves 30-μV/mA load regulation while consuming 120-μA quiescent current. The measured undershoot/overshoot and the corresponding settling time with a 450-mA/100-ns load current step are 55 mV and 174 ns and 56 mV and 220 ns, respectively. The figure of merit (FoM) is as low as 0.0073 ps.