Bus Width Research Articles

Spatial Structure of Places in Singapore from a Complexity Perspective of the Public Transport Network

As cities become increasingly developed, inclusive and equal provision of public services and affordable housing is essential in achieving sustainable growth and development. In Singapore, with much of the population living in public housing and taking public transport, there is a great need to understand their landscape across the country. In this study, using tools from Complexity Science, we elucidated the spatial organization of places in Singapore through public bus transport connectivity, and investigated the association between such pattern to the distribution of the population age groups and property price. From the spatial network of the public transport services, we probed the places’ scale using the continuum percolation approach to uncover their spatial pattern. After that, we employed an information-theoretic measure of complexity to quantify the spatial organization of the system. The results show that there is a critical distance embedded within the public transport system at which the structure of the places in Singapore emerges. In many areas, the connectivity between places map well, and are greatest within the official planning boundary, demonstrating the influence of upstream spatial planning in determining bus networks. Yet in mature towns (particularly those in the central region), bus connectivity spans beyond planning boundaries, suggesting a more organic pattern on the ground in places with a longer history of development. The complexity of the bus network maps remarkably well to residential areas, and was associated with the distribution of resident age groups, and to property prices. In particular, the well-connected areas in and around the central region of Singapore are associated with higher property price and an older population. In contrast, the peripheral less-connected areas tend to see a lower property price and a younger population. The findings can contribute to understanding the existing pattern of physical and social form within an urban system, highlighting the role of complexity science methods in uncovering ‘emergent’ patterns in bus transport networks, beyond initial spatial plans, as areas mature over time. It can also guide future planning by highlighting the areas where more attention is needed to enhance island wide public bus connectivity, and by doing so, enable the public transport system to contribute to reducing potential socio-economic polarization within the system.

A novel digital sensor-less synchronous rectification method for CLLLC resonant converters

With the rapid development of the renewable energy vehicles, pursuing the power converters with high efficiency and high reliability has caught more attention recently. In order to solve those problem with low cost, this paper proposes a sensor-less synchronous rectification method for the CLLLC resonant converters. The precise conduction time of the synchronous switches is obtained based on the analysis of the working principle of CLLLC resonant converter, and the relationship between the SRs switching time and the inverter switching time can be derived as well. To achieve the wide output voltage range, the converter requires wide working frequency. And the correct turn-on and turn-off time for the synchronous switches can be obtained respectively by calculation and piecewise linear function fitting methods within full working frequency range. Compared with traditional synchronous rectification control for CLLLC, which require additional high bandwidth voltage sensors or current sensors, the method proposed in this paper is realized by only one low-cost output voltage sensor. And the proposed method is suitable for high-power applications with a wide voltage and load variation. Moreover, because of the symmetrical topology, this method is valid in bidirectional power transfer. Additionally, the exist analog synchronous rectification control chips suffer from losing accuracy with wide bus voltage variation, however, this method can overcome this shortcoming. Thus, the proposed synchronous rectification method is a low-cost and suitable for high-power, high power density, high efficiency application which benefit from its simple algorithm. Finally, the proposed sensor-less synchronous rectification method is validated by the simulation results and experimental results. The results of simulation and experimental have shown the proposed method offers significant benefits which increases the efficiency of the whole CLLLC system by about 3%, and the reliability of the converter are greatly increased, due to the cooler SRs.

A Two-Stage DC/DC Isolated High-Voltage Converter with Zero-Voltage Switching and Zero-Current Switching Applied in Electronic Power Conditioners

This paper presents a two-stage DC/DC converter with high efficiency utilized in an electronic power conditioner (EPC), which is widely applicable in satellite communications, etc. The galvanically isolated converter contains two cascaded converters: a buck converter, which is a pre-regulator operating under a closed-loop condition, and a push–pull converter, which is intended to boost the input voltage, operating under an open-loop condition. In the push–pull converter, the power switches, including the main switches and the rectifier diodes, operate under zero-voltage switching (ZVS) and zero-current switching (ZCS) at both switch off and switch on, which minimizes the switching loss. Furthermore, all of the parasitic parameters, such as the parasitic capacitance, leakage inductance, and magnetizing inductance of the main transformer, are fully utilized. Therefore, the presented topology benefits from fewer semiconductors but higher efficiency. The proposed topology produces less EMI noise because of ZVS and ZCS processes whose fundamental switching frequency interference is relatively low. The presented converter achieves a wide bus voltage regulation range in a satellite because of the pre-regulation of the buck cell. The theoretical analysis is validated by a prototype and its experimental results. The maximum efficiency of the converter can be up to 94.5%, and the high-voltage output is 7000 V.

Multisource data integration for targeted bus exterior advertising

Bus exterior advertising plays a significant role in outdoor advertising, since it provides frequent exposure to a large number of residents. Traditional route selection methods are generally based on a rough estimation, for example, the number of total passengers of a bus route or the geographical features along the bus route. Targeted bus exterior advertising remains a challenge as little is known about the characteristics of the people along the bus route. In this study, we are aiming at determining a set of bus routes for a given ad category to maximize advertising effectiveness, by mining multiple data sources, including mobile phone data, bus GPS data, smart card data (SCD), and land use data. Specifically, we first estimated the distribution of potential target audiences using mobile phone data and land use data. Two optimization models are proposed considering different advertising requirements. For well-established brands that audiences are familiar with, a wide coverage-oriented bus route selection model is proposed to maximize the coverage of potential target audiences. For new brands that require a high level of exposure before they become recognizable, a deep coverage-oriented bus route selection model is proposed to maximize the total exposure times of the ads. Both models were demonstrated with a case study in Shenzhen, China to explicitly present the outcomes of the models and the differences between them. The calculation results show that the wide coverage-oriented model achieves an average of 84.8% improvement compared with baseline 1 which selects the bus routes with the most passengers, while an average of 9.2% improvement compared with baseline 2 which selects the bus route with the maximum coverage of the target area in reaching more potential target audiences. The exposure intensity of the deep coverage-oriented model is almost 3.7 times of the wide coverage-oriented model. The proposed models provide new options for advertisers to select a suitable advertising strategy according to their needs.

Trans_Proc

A reconfigurable transform processor is proposed and implemented here. Firstly, a brief study of processors implementing different transformations is presented. We have categorized the transform processor as the one which can implement a number of linear transforms using reconfigurability. The theoretical suitability regarding the architecture of the processor is proved by graph theory method. Then the complete architecture of the overall processor and the processing element is presented and implemented using VHDL. The complete instruction set suitable to the processor is designed. The instructions are mapped to the sequence of control signals. Generating sequence of control signals for every type of instructions would finally create a hardwired control unit for the processor which was also presented. Next the processor is fed with data to simulate it. A three-phase simulation is carried out to prove the correctness of the design. Finally the same processor with a data bus width of 32 to 512 is implemented and compared in terms of speed and size.

Technology Strategy for Meticulous Governance of Smart Cities: Memory Bus Width Aware Pruning for Efficient Image Super-Resolution Implementation in FPGA

The mega-city governance is based on the aggregation, collation, development and application of multi-scene data, and efficient access to scene data is a key link to promote the meticulous governance of smart cities. Super-resolution technique is the process of upscaling and improving the details within an image. In this paper, we implement a 16-layer residual neural network (ResNet) for the efficient image super-resolution in FPGA. We discover that the memory access is the major performance bottleneck of this implementation. To reduce the memory access overhead, we design a pruning algorithm with the consideration of the memory bus width. Since the memory used in our design generates 256 bits for each access, the proposed pruning algorithm drops the kernel by aligning this bit width. That is, all kernels in one layer are ranked by its L1-norm and we drop the kernels out of the 256 bits. The experimental results show that the proposed method reduces the number of weights by 50% compared with the baseline. As a result, the inference speed can be enhanced by 3 times.

The Torque Ripple Optimization of Open-Winding Permanent Magnet Synchronous Motor With Direct Torque Control Strategy Over a Wide Bus Voltage Ratio Range

Due to the battery voltage performance of the dual power supply open-winding permanent magnet synchronous motor (OW-PMSM) system in electric vehicles, the dc bus voltages of the dual power supply varies and the traditional direct torque control (DTC) method will not be suitable and may lead to obvious torque ripples. Thus, in this article, based on the analysis of the effect of voltage vector on torque variation, a bus voltage ratio is employed in the switching table optimization strategy of DTC for OW-PMSM, the voltage vector selection method is also modified according to different voltage ratio, and then, the optimized control scheme for OW-PMSM over a wide bus voltage ratio is achieved to diminish the torque ripples. Finally, simulation models of the proposed method are built to verify the theory, and the corresponding experiments are also conducted to verify the feasibility and effectiveness of the proposed optimized control strategy.

Minimizing Off-Chip Memory Access for CNN Accelerators

Convolution neural network (CNN) accelerators are commonly used to boost the CNN application's performance. The energy efficiency of the CNN accelerators is of paramount importance for battery-operated devices like smartphones. A substantial fraction of their energy consumption is due to off-chip memory accesses. These accelerators connect to the off-chip memory by a wide bus to improve the throughput. However, accessing the data from an unaligned address or size that is not a multiple of bus width leads to low bus width utilization and wastage of energy. Memory accesses can be reduced considerably by partitioning the data in a way that increases the number of aligned accesses and optimally utilizes bus width. We propose an approach that factors in the architectural parameters to evaluate the memory access. Our tool determines optimal partitioning and data reuse scheme for convolution and fully connected layers to minimize the off-chip memory accesses for these accelerators. Compared to state-of-the-art, our approach reduces off-chip memory accesses of AlexNet, VGG16, and ResNet:50 by 9%, 16%, and 28% on 64 bits data bus and by 16%, 29%, and 46% on 128 bits data bus, respectively.

Analysis of gallium nitride-based optical microring resonator with doped polymer grafting material

<p>In this paper, the Gallium nitride-based optical microring resonator (OMR) filter with polymer grafting material (PMMA) coating was designed and optimized to predict its potential as a wavelength filtering device. The optimization was focused on the design parameters such as polymer thickness, gap separation variation, and the bus and ring waveguide widths. The target is to achieve the best output in terms of insertion loss (IL) and Extinction Ratio for wavelength-division multiplexing (WDM) applications, specifically for the use of the C-Band network. Upon completion, it was found that the optimized design was a ring radius of 10 μm and PMMA thickness of 0.055 μm, with the bus waveguide width of 800 nm and the output bus waveguide of 800 nm giving the observed IL of 0.07 dB and 87.3% extinction rate.</p>

Voltage Sharing With Series Output Connected Battery Modules in a Plug-and-Play DC Microgrid

This article presents output voltage sharing among series output connected battery power modules (BPMs) in plug-and-play (PnP) dc microgrids with a wide bus voltage range. The system provides active cell balancing and interfaces cells to the bus voltage through series output connected BPMs. A cell current sensor is utilized to achieve both state-of-charge regulation and output voltage sharing. To improve microgrid modularity, the battery pack behaves as a current source. A current-dependent droop between the individual output voltages and input currents is used to facilitate series output connected voltage sharing with bidirectional power flow, simple control, and smooth transitions between charge and discharge regions. Experimental results are reported for a 3 kWh 1C-rate prototype consisting of two parallel 24 V subsystems, with five series output connected BPMs in each subsystem. Each BPM consists of three battery cells and three 100 W dc-dc converters.

Design of RISC-V CPU for 100 Gbps Network Application

<p indent=0mm>As a new open-source reduced instruction set architecture, RISC-V has advantages of low power consumption, small area and high performance. Therefore, technology and products based on RISC-V are developing rapidly. However, currently there are few medium and high end 64 bit CPU design instances based on the RISC-V architecture, and it is also hard to find corresponding commercial IP, especially for high-speed network applications. In this paper, we firstly improved the open source 64 bit U500 RISC-V SoC by extending the Bus width and adding L2 Cache, and etc. Secondly we implemented a complete 100 Gbps Ethernet function, which includes MAC, PCS, and SerDes, and the TX buffer and RX buffer used for the function. Finally we proved correctness and effectiveness of entire 64 bit RISC-V CPU design and 100 Gbps Ethernet function by simulation, FPGA verification and boot of Linux operation system. The designed RISC-V CPU and 100 Gbps Ethernet function can be applied to data center application such as smart network interface cards.

Pareto optimal design space exploration of cyber-physical systems

Cyber-physical systems (CPS) integrate a variety of engineering areas such as control, mechanical, and computer engineering in a holistic design effort. While interdependencies between the different disciplines are key attributes of CPS design science, little is known about the impact of design decisions of the cyber part on the overall performance qualities of the system. To investigate these dependencies, this paper proposes a simulation-based Design Space Exploration (DSE) framework that considers detailed cyber system parameters such as cache size, bus width, and voltage levels in addition to physical and control parameters of the CPS. We propose a DSE algorithm that explores the parameter configurations of the cyber-physical sub-system in order to approximate the Pareto-optimal design points with respect to design objectives such as energy consumption and control stability. For validation, we have successfully applied the proposed framework to an inverted-pendulum application. Here, our holistic evaluation of the Pareto-optimal points reveals the presence of non-trivial trade-offs that are imposed by the control, physical, and detailed cyber parameters. For instance, the identified energy and control optimal design points comprise configurations with a wide range of CPU speeds, sampling rates, and cache configurations following non-trivial zigzag patterns. The proposed framework could identify and manage these trade-offs and, as a result, is an imperative first step to automate the search for superior cyber-physical system configurations.

Game Theoretical Approach to Novel Reactive Power Ancillary Service Market Mechanism

In deregulated power systems, reactive power ancillary service through electricity market is becoming relevant where private generation companies participate in maintaining system wide bus voltage within the permissible limits. Marginal cost price (MCP) based real time reactive power ancillary service market faces several challenges due to the localized nature of reactive power. In this paper, a market mechanism for real time reactive power ancillary service market based on Stackelberg game model is proposed considering voltage-apparent power coupled subsystems. In the proposed Stackelberg game model, Independent System Operator (ISO) is considered as the leader, and GENCOs as followers. In the formulation, each GENCO is associated with a relevance factor in the partitioned subsystem so as to consider the real time voltage support requirement in the system. The market is then formulated as Mathematical Program with Equilibrium Constraints problem (MPEC). Existence of equilibrium, incentive compatibility, and individual rationality of the proposed market mechanism is then analysed in this work. The numerical examples are illustrated in PJM 5-bus system, and tested on IEEE 30- bus system, and Nordic 32 Bus-system. The mechanism induces truth-telling behavior of GENCOs, yields a non-negative profit, and the system wide bus voltage is improved.

A Novel Hybrid PFM/IAPWM Control Strategy and Optimal Design for Single-Stage Interleaved Boost-LLC AC–DC Converter With Quasi-Constant Bus Voltage

Single-stage boost-LLC ac-dc converters have been a popular soft-switched topology because of the high-efficiency and being cost-effective. However, low power capacity is its main disadvantage. In this article, a novel single-stage interleaved boost-LLC ac-dc converter with higher power capacity is presented while achieving the low input current ripple. However, it still suffers from the wide and high bus voltage for universal operation, as a result of the conventional pulse frequency modulation (PFM) with the duty cycle of 0.5. Furthermore, this wide bus voltage will bring the difficulties in designing the LLC resonant cell. To solve these issues, a dual-loop feedback control strategy based on PFM/interleaved asymmetric pulsewidth modulation hybrid modulation and power balance based optimal design are proposed. With the proposed control strategy and optimal design, the bus voltage of the studied converter is not only significantly reduced, but also zero voltage switching for the primary switches and zero current switching for the secondary diodes are still maintained. Thus, the higher efficiency can be achieved. Operation principles and control scheme for the studied converter are fully addressed. The optimal design based on power balance principle is also discussed in this article. A 300 W prototype is fabricated to validate the theoretical analysis and optimal design. The experimental results demonstrate the prototype can simultaneously obtain the universal operation with high power factor above 0.98 and the quasi-constant bus voltage below 500 V. The measured peak efficiency is 92.7% under 115 Vac input voltage at full load.

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

Mapping TSN Traffic Scheduling and Shaping to FPGA-Based Architecture

Time-Sensitive Networking (TSN), which evolves from the Ethernet standards, has been developed to ensure deterministic transmission in data networks. Asynchronous Traffic Shaping (ATS) extends the conventional synchronized TSN with an asynchronous scheduler to guarantee a bounded transmitting delay. In this work, we present a Field Programmable Gate Arrays (FPGA) implementation of a TSN scheduling entity, which leverages ATS for the frame forwarding process. We explore the ATS design by function blocks and compare it with a benchmark design utilizing strict-priority scheduling. In terms of operating frequency, our results indicate that strict-priority scheduling performs 1.05% to 9.56% higher maximum frequency than ATS with the same configurations. Regarding resource utilization, ATS consumes 51% to 119% more logic blocks and 51% to 101% more registers than strict-priority scheduling. Based on the synthesis and fitting results from Register-Transfer Level (RTL) simulations, we provide a general vision of designing and implementing considerations of the ATS function. Specifically, we show the influences of the buffer and bus width configuration on the FPGA implementation scale and data rate.

Analysis and Optimization design of the column bus parasitic effects on large-array CMOS image sensor

This paper analyzes the impact of column bus parasitic parameters on the output noise and response speed of the pixel signal in large-array CMOS image sensor (CIS), and the optimized column bus design scheme has been obtained. By building the mathematical model of the column bus, the relationship between output noise, response speed and the size of the column bus is revealed, and the influence of the column bus size on the sensor is evaluated by system impact factor (SIF). In 110 ​nm CMOS process and a 12.45 ​cm ​(H) ​× ​12.45 ​cm ​(V) pixel array, the double-ended readout architecture is utilized for output noise and response time analysis. Average output noise (146 ​μV) and response time (6.35 ​μs) are attained at column bus width of 0.5 ​μm. The experimental results show that for a given pixel array, the increase of the column bus width will cause output noise reduction and a longer response time. In the chip design, the column bus size could be optimized according to the relationship between output noise, response speed and pixel array size given in the paper.

High-performance version of the RPB code based on graphic processors for determination of the plasma boundary in tokamaks

The operation of modern tokamaks is impossible without an effective system for controlling the plasma boundary during the discharge. In this paper, we consider a method for determining the plasma boundary on the basis of integral equations. A high-speed parallel code using GPUs was developed for this purpose. Different methods of parallelization of the algorithm have been considered. The possibility of processing the magnetic measurements in real time during experiments is shown. The effect of the technical parameters of GPUs (the number of cores, the data bus width, the amount of internal memory) on the performance is also shown. The simulation results for the T-15MD tokamak, currently under construction at National Research Center Kurchatov Institute, are presented.

Forming and Co-simulation of Square and Triangular Waveforms by Using System Generator

Nowadays Field Programmable Gate Arrays(FPGAs) are used to implement several processes in different areas such military defense, medical devices, automation, telecommunication, and image processing etc. Some of the advantages of FPGA are parallel and hardware processing. On the other hand programming FPGAs by classic design methodologies requires much effort. Therefore, design tools like System Generator can provide facilities about programming FPGAs. System Generator is a design tool from Xilinx to program the Xilinx FPGAs in MATLAB/Simulink graphic based editor. Also its block set is limited with respect to Simulink, has. In this study square, and triangular waveforms are built with the basic blocks of System Generator tool. These waveforms belong to basic sources for signal processing. Generally, they are used in power electronics especially for producing PWM, or sinus PWM. Also co-simulation can be done by using System Generator. Square waveform block, which is implemented, has variable amplitude, frequency, duty cycle, and offset values whereas triangular waveform has variable amplitude, frequency, and offset values. Triangular waveform has an error as 2 % due to data bus width.

Fast Transaction-Level Model for Direct Memory Access Controller

Transaction-Level Modeling (TLM) has been widely used in system-level design in the past few years. Simulation speed of Virtual Platforms (VPs) depends mainly on the transactions which are initiated by the Programmer’s View (PV) models of the VP devices. PV models are required to run at highest simulation speed. Data bus width as a hardware (HW) parameter should not reduce simulation speed of the modeled transactions. Furthermore, HW-related parameters should only be accounted for when considering timing of the models. A fast SystemC-TLM model is developed for the widely used ARM PrimeCell PL080 DMAC IP. The performance of the proposed model is validated against a developed RTL model for the same device. The effect of the transactions granularity on simulation speed is determined. Different programmed transfers are simulated and compared with open-source Quick Emulator (QEMU)-based models. The developed model is compared with the developed RTL, the open-source QEMU model, and the existing ARM Fast Model (AFM). It is shown that simulation time of the developed model is reduced by two orders of magnitude as compared to the other existing models.