Wear-leveling Scheme Research Articles

APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Due to high static power and low scalability, the traditional SRAM-based cache is not a good solution for image processing applications. Emerging Spin Transfer Torque Magnetic RAM (STT-MRAM) is a promising candidate for cache due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. Therefore, by making use of the ability of tolerating minor errors in image processing applications, this work presents an STT-MRAM based APProximate cache architecture (APPcache+) to write/read approximate data, which can largely reduce the cache energy and improve the STT-MRAM lifetime. APPcache+ includes three main designs. Firstly, we find that there are many similar elements (e.g., pixels in images) in cache lines. Therefore, APPcache+ presents several lightweight similarity-based encoding techniques to remove redundant elements, thus shortening the data size and reducing the energy of STT-MRAM cache. Secondly, we design a partial read scheme to reduce the read energy of the STT-MRAM cache. In the traditional decompression process, the whole line is fetched into the decompressor, leading to unnecessary read energy. The partial read scheme can largely reduce read energy while keeping the overhead low. Thirdly, we observe the encoding schemes may lead to bit write imbalance. Therefore, we propose a lightweight Ping-Pong intra-line wear-leveling scheme to improve the lifetime. Compared with the baseline, extensive evaluation results show that our APPcache+ can largely reduce the overall energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation and 1.86% output quality loss.

V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent Memory

Benefiting from numerous attractive characteristics, persistent memory (PM) has become a promising substitute for DRAM. Unfortunately, PM suffers from limited endurance of memory cells, especially with the unbalanced wears induced by applications. Even though several wear-leveling aware allocators have been proposed to prolong the lifespan of PM, they fail to perceive the endurance variation among memory cells, which may severely damage the weak cells. In this paper, we propose V-WAFA, a fine-grained PM allocator that considers endurance variation to improve the lifespan of PM. First, V-WAFA adopts a priority-based wear-leveling strategy to mitigate the side-effect of endurance variation among pages. Second, V-WAFA utilizes fine-grained space management and allocation strategy inside pages. Briefly, V-WAFA divides pages into basic units and allocates the basic units of a page in a rotational manner to evenly distribute fine-grained updates on memory cells. We implement V-WAFA in Linux 4.4.4 and evaluate it by running standard workloads on Redis, a typical in-memory key-value store. Evaluation results show that the wear-leveling effect of V-WAFA exceeds that of malloc, nvm_malloc, WAlloc, NVMalloc, and WAFA for 7.02×, 6.91×, 5.7×, 5.68×, and 3.78×, respectively. V-WAFA also achieves similar performance with state-of-the-art PM allocators on Redis running YCSB workloads.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Low power and high I/O efficiency hybrid memory for Internet of Things edge devices

The performance of the Internet of Things (IoT) devices is gradually improving. However, traditional memory devices cannot meet the requirements of IoT devices in terms of energy consumption, capacity, I/O efficiency, and so on. This paper proposed a hybrid storage class memory architecture, which uses phase-change memory (PCM) and dynamic random-access memory (DRAM) to form a hybrid structure that is managed by a hybrid memory controller and an in-memory file system. A dynamic page row buffer miss migration (DPRM) algorithm is proposed to optimize for hybrid memory to reduce the negative impact on PCM. A wear-leveling scheme is added to the persistent in-memory file system to make the write access in PCM more dispersed, improving the reliability of the storage system. Experimental results show that the energy consumption of the memory system can be reduced by 47.57%, and the I/O efficiency has increased by 9.57 times when compared to the traditional memory systems of IoT devices.

Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs

Static random access memory (SRAM) based field-programmable gate array (FPGA) is currently facing challenges of high leakage power and limited capacity. Replacing SRAM in FPGA with emerging nonvolatile memory (NVM) has become an effective way to solve this issue. While enjoying the advantages of NVM in power consumption and integration, nonvolatile FPGA platform is also plagued by lifetime problem. Among all components, block random access memory (BRAM) has the severest endurance problem. The state-of-the-art wear leveling strategies for NVM-based BRAMs rely heavily on static analysis. However, the static analysis would not be accurate enough for application with multiple runtime working patterns. In this article, we propose a pattern-aware wear leveling mechanism. It can improve lifetime through adaptive reconfiguration without static analysis. Evaluation shows that our mechanism can achieve 120% higher lifetime improvement with 4% performance overhead than existing performance-aware wear leveling strategy (Huai et al., 2019).

Tnvmalloc: A Thread-Level-Based Wear-Aware Allocator for Nonvolatile Main Memory

The nonvolatile main memory (NVMM) has the advantages of near-DRAM speed, byte-addressability, and persistence, and presents limitations in write durability. The memory allocator, a fundamental data structure of memory management, can effectively mitigate the wear speed, thereby prolonging the NVMM lifetime. Nevertheless, balancing the performance and writing reliability in single and multi-thread scenarios is still an open problem for NVMM allocators. In this paper, we propose a thread-level wear-aware allocator (Tnvmalloc) that divides the NVMM space into multiple management granularities and then dynamically selects the optimal blocks using a wear-leveling strategy based on allocation requests and wear records. Experiments show that the proposed Tnvmalloc provides more than 10 times improvement in wear-leveling than typical allocators Glibc malloc, NVMalloc, and nvm_malloc, which becomes obvious especially in multi-threaded scenarios. Moreover, when allocating large memory blocks, Tnvmalloc achieves three times faster than that of NVMalloc.

An SVM-Based NAND Flash Endurance Prediction Method.

NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.

AxFTL: Exploiting Error Tolerance for Extending Lifetime of NAND Flash Storage

NAND flash storage has become a standard choice in consumer electronics and is gaining popularity in enterprise systems due to its superior performance and low-power consumption. While its cost disadvantage is rapidly fading thanks to multibit cell technologies and 3-D stacking architectures, the challenge of limited endurance is still lingering and is expected to become more daunting as bits-per-cell continues to increase. In this article, we propose a novel flash translation layer (FTL) design named AxFTL (Approximate FTL) that extends the lifetime of NAND flash storage for error-tolerant applications. For error-tolerant data, AxFTL adopts shallow erase that lowers erase voltage to reduce the erase-induced wearing at the cost of an increased error rate. AxFTL manages multiple groups of blocks by error rates and allocates them according to the error tolerance of write requests. The key components of AxFTL include error tolerance-aware garbage collection and wear leveling schemes that manage the blocks with different error rates with minimal overhead. We implement AxFTL in an SSD simulator for the evaluation of the lifetime improvement and the actual allocation of the blocks. For application-level evaluation, we apply AxFTL to compressed video storage and evaluate the quality of video playback. Our experimental results show that AxFTL greatly improves the lifetime of NAND flash storage by 61% while maintaining a high structural similarity (SSIM) of 0.86 as compared to the conventional FTL.

Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs

Since static random access memory (SRAM)-based field-programmable gate array (FPGA) has limited density and comparatively high leakage power, researchers have proposed FPGA architectures based on emerging nonvolatile memories (NVMs) to satisfy the requirements of data-intensive and low-power applications. Among all components, block random access memory (BRAM) has the severest endurance problem in FPGA. Unluckily, traditional wear leveling (TWL) strategies cannot be directly applied to nonvolatile FPGA because it may induce large performance overhead. In this article, we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies pertaining to coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl) are developed to balance inter-BRAM and intra-BRAM writes. Procedures, including static analysis, wear leveling-guided placement, and reconfiguration are discussed. A supportive circuit design is proposed, too. The evaluation shows that C-Pearl and F-Pearl can achieve 34% and 46% higher lifetime improvement and simultaneously 8% and 11% lower performance overhead than TWL.

SREA: A self-recovery effect aware wear-leveling strategy for the reliability extension of NAND flash memory

With aggressive scaling and multilevel cell technology, the reliability and lifetime of the NAND flash degrades. To address this issue, a Self-Recovery Effect Aware (SREA) strategy is proposed to extend the storage reliability of the NAND flash. The key purpose of SREA is a wear-leveling strategy based on the self-recovery effect of the NAND flash. First, this study verifies the self-recovery effect of the NAND flash based on our hardware-software codesigned experimental platform; then, we propose the concept of relaxation time (tr). The change rule of the data retention error under different degrees of tr for blocks subjected to different program/erase (P/E) cycles is also investigated. The experimental results show that there is an approximately 60% gap of retention error rate when tr = 0 h and tr = 6 h after the same retention time. In addition, we apply the experimental rules to the wear-leveling strategy. Compared with the traditional wear-leveling strategy that does not consider tr, the maximum data reliable retention time of SREA can be extended by 2.67×.

LiwePMS

Next-generation Storage Class Memory (SCM) offers low-latency, high-density, byte-addressable access and persistency. The potent combination of these attractive characteristics makes it possible for SCM to unify the main memory and storage to reduce the storage hierarchy. Aiming for this, several persistent memory systems were designed. However, the heavy metadata and transaction cost degrade the system performance. Moreover, neither of them pays attention to wear-leveling strategy. In this article, we present a lightweight persistent memory system, LiwePMS, which allows a fast access to persistent data stored in SCM with wear-aware memory management. LiwePMS makes performance improvement by simplifying the metadata management and the consistency method. LiwePMS abstracts SCM as heap space with container-based dynamic address mapping. Also, LiwePMS implements efficient wear-aware dynamic memory allocator and lightweight transaction mechanism for data consistency in user-space library. The experiments showed that LiwePMS persists key-value records 1.5× faster than Redis RDB mechanism. LiwePMS improves the performance of persistent region operation by more than 45%, 63%, and 1.1× comparing with HEAPO, Mnemosyne, and NVML, respectively. Also, the wear-leveling policy of memory allocator outperforms that of NVMalloc from 35% to 30%, and the transaction method promotes the transaction performance to 1.8× compared to NVML.

Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory

With the rapid development of technology scaling and cell density improvement for capacity increase and cost reduction, nand flash memory is confronted with degraded reliability. On one hand, while low-density parity-check (LDPC) codes have been deployed in today's nand flash memories to enhance reliability, flash read latency has still been a performance bottleneck with the increased raw bit error rates (RBER). On the other hand, significant process variations (PV) have been found on existing nand flash memories, which introduce great reliability variations among different flash blocks. Recent studies have proposed to exploit PV to improve endurance by better wear leveling or to improve write performance. These approaches are prone to allocate read data to blocks with low reliability, which further degrades read performance. This paper proposes to enhance read performance of LDPC-equipped nand flash memory by exploiting the reliability variations from PV. The paper consists of three parts. First, a block grouping approach is presented to categorize flash blocks according to their reliability. Second, according to the grouping scheme, a data placement scheme is proposed, which allocates read-hot data to flash blocks with high reliability. At the same time, the read-cold data is moved to blocks with low reliability. As a result, the read performance is enhanced. However, allocating high reliable blocks for read-hot data collides with previous PV-based wear leveling methods. To address the issue, the third part is a grouping partition scheme which limits the amount of high reliable blocks occupied by read-hot data. Therefore, read performance enhancement can be achieved and the wear leveling schemes will be impacted slightly. Experiment results present that, the proposed approach can provide significant read performance improvement on LDPC-equipped nand flash memory and is compatible with the previous PV-based wear leveling.

Enhancing security of NVM-based main memory with dynamic Feistel network mapping

As promising alternatives in building future main memory systems, emerging non-volatile memory (NVM) technologies can increase memory capacity in a cost-effective and power-efficient way. However, NVM is facing security threats due to its limited write endurance: a malicious adversary can wear out the cells and cause the NVM system to fail quickly. To address this issue, several wear-leveling schemes have been proposed to evenly distribute write traffic in a security-aware manner. In this study, we present a new type of timing attack, remapping timing attack (RTA), based on information leakage from the remapping latency difference in NVM. Our analysis and experimental results show that RTA can cause three of the latest wear-leveling schemes (i.e., region-based start-gap, security refresh, and multi-way wear leveling) to lose their effectiveness in several days (even minutes), causing failure of NVM. To defend against such an attack, we further propose a novel wear-leveling scheme called the ‘security region-based start-gap (security RBSG)’, which is a two-stage strategy using a dynamic Feistel network to enhance the simple start-gap wear leveling with level-adjustable security assurance. The theoretical analysis and evaluation results show that the proposed security RBSG not only performs well when facing traditional malicious attacks, but also better defends against RTA.

Endurance-Aware Security Enhancement in Non-Volatile Memories Using Compression and Selective Encryption

Emerging non-volatile memories (NVMs) are notable candidates for replacing traditional DRAMs. Although NVMs are scalable, dissipate lower power, and do not require refreshes, they face new challenges including shorter lifetime and security issues. Efforts toward securing the NVMs against probe attacks pose a serious downside in terms of lifetime. Cryptography algorithms increase the information density of data blocks and consequently handicap the existing lifetime enhancement solutions like Flip-N-Write. In this paper, based on the insight that compression can relax the constraints of lifetime-security trade-off, we propose CryptoComp, an architecture that, taking the advantage of block size reduction after compression, aims to enhance the memory system lifetime and security. Our idea is to limit the avalanche effect caused by encryption algorithms in a lower space through compression and selective encryption. This way, for highly compressible data blocks, we follow a fully-encryption approach while for poorly compressible data blocks, we rely on a non-deterministic fine-grain selective-encryption mechanism. Additionally, a simple and block-oriented wear-leveling scheme is presented to fairly distribute the bit flips on memory cells. Our experimental results show 3.59 $\times$ and 3.66 $\times$ lifetime improvements over two state-of-the-art schemes, DEUCE and i-NVMM, while imposing a negligible performance degradation of 2.1 percent, on average.

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

비휘발성 메모리 기반 캐시의 쓰기 작업 최적화를 위한 캐시 시뮬레이터 설계

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

SWANS

NAND flash memory–based solid state disks (SSDs) have been widely used in enterprise servers. However, flash memory has limited write endurance, as a block becomes unreliable after a finite number of program/erase cycles. Existing wear-leveling techniques are essentially intradisk data distribution schemes, as they can only even wear out across the flash medium within a single SSD. When multiple SSDs are organized in an array manner in server applications, an interdisk wear-leveling technique, which can ensure a uniform wear-out distribution across SSDs, is much needed. In this article, we propose a novel SSD-array level wear-leveling strategy called SWANS ( &lt;u&gt;S&lt;/u&gt; moothing &lt;u&gt;W&lt;/u&gt; ear &lt;u&gt;A&lt;/u&gt; cross &lt;u&gt;N&lt;/u&gt; &lt;u&gt;S&lt;/u&gt; SDs) for an SSD array structured in a RAID-0 format, which is frequently used in server applications. SWANS dynamically monitors and balances write distributions across SSDs in an intelligent way. Further, to evaluate its effectiveness, we build an SSD array simulator on top of a validated single SSD simulator. Next, SWANS is implemented in its array controller. Comprehensive experiments with real-world traces show that SWANS decreases the standard deviation of writes across SSDs on average by 16.7x. The gap in the total bytes written between the most written SSD and the least written SSD in an 8-SSD array shrinks at least 1.3x.

A page-granularity wear-leveling (PGWL) strategy for NAND flash memory-based sink nodes in wireless sensor networks

Sink nodes are the data centers of wireless sensor networks (WSNs), and the storage management scheme for such nodes is vital, particularly in applications such as wireless multimedia sensor networks that involve the collection of massive amounts of data. NAND flash memory is often employed in sink nodes because of its excellent characteristics. Because the lifetime of NAND flash memory is highly restricted by the bit error rate (BER), we present a novel page-granularity wear-leveling (PGWL) strategy to extend the lifetime of NAND flash memory. The concept of PGWL is motivated by two main experimental observations obtained from our own experimental platform for NAND flash memory: first, the raw bit error rate (RBER) distribution exhibits a distinct variance in endurance among different pages, and this variance is more significant than that among different blocks; second, programming relief operations (consisting of only erasing, not programming) can clearly reduce both program-disturb and retention errors. In this study, we first present a practical average RBER prediction model to evaluate the reliability of flash pages using the system clock of the sink node. Thus, the PGWL strategy enables self-adaptive leveling of the RBER growths of different pages in real time by introducing page-granularity wear leveling instead of block-granularity wear leveling to exploit the lifetime potency of each page in a block. Experimental results show that PGWL can extend the lifetime of 2×-nm NAND flash memory by 88.3% compared with traditional bad block management (BBM), while experiencing at most a 0.85% degradation in data throughput speed compared with the conventional sector mapping scheme.

Durable Address Translation in PCM-based Flash Storage Systems

Phase change memory (PCM) is a promising DRAM alternative because of its non-volatility, high density, low standby power and close-to-DRAM performance. These features make PCM an attractive solution to optimize the management of NAND flash memory in embedded systems. However, PCM's limited write endurance hinders its application in embedded systems. Therefore, how to manage flash memory with PCM-particularly guarantee PCM a reasonable lifetime-becomes a challenging issue. In this paper, we propose to partially replace DRAM using PCM to optimize the management of flash memory metadata for better system reliability in the presence of power failure and system crash. To prolong PCM's lifetime, we present a write-activity-aware PCM-assisted flash memory management scheme, called PCM-FTL. By differentiating sequential and random I/O behaviors, a novel two-level mapping mechanism and a customized wear-leveling scheme are developed to reduce writes to PCM and extend its lifetime. We evaluate PCM-FTL with a variety of general-purpose and mobile I/O workloads. Experimental results show that PCM-FTL can significantly reduce write activities and achieve an even distribution of writes in PCM with very low overhead.

Heating Dispersal for Self-Healing NAND Flash Memory

Substantially reduced lifetimes are becoming a critical issue in NAND flash memory with the advent of multi-level cell and triple-level cell flash memory. Researchers discovered that heating can cause worn-out NAND flash cells to become reusable and greatly extend the lifetime of flash memory cells. However, the heating process consumes a substantial amount of power, and some fundamental changes are required for existing NAND flash management techniques. In particular, all existing wear-leveling techniques are based on the principle of evenly distributing writes and erases. For self-healing NAND flash, this may cause NAND flash cells to be worn out in a short period of time. Moreover, frequently healing these cells may drain the energy quickly in battery-driven mobile devices, which is defined as the concentrated heating problem. In this paper, we propose a novel wear-leveling scheme called DHeating (Dispersed Heating) to address the problem. In DHeating, rather than evenly distributing writes and erases over a time period, write and erase operations are scheduled on a small number of flash memory cells at a time, so that these cells can be worn out and healed much earlier than other cells. In this way, we can avoid quick energy depletion caused by concentrated heating. In addition, the heating process takes several seconds and has become the new performance bottleneck. In order to address this issue, we propose a lazy heating repair scheme. The lazy heating repair scheme can ease the long time delays caused by the heating via delaying the heating operation and using the system idle time to repair. Furthermore, the flash memory's reliability becomes worse with the flash memory cells reaching the excepted worn-out time. We propose an early heating strategy to solve the reliability problem. With the extended lifetime provided by self-healing, we can trade some lifetimes for reliability. The idea is to start the healing process earlier than the expected worn-out time. We evaluate our scheme based on an embedded platform. The experimental results show that the proposed scheme can effectively prolong the consecutive heating time interval, alleviate the long time delays caused by the heating, and enhance the reliability for self-healing flash memory.