Low power and high I/O efficiency hybrid memory for Internet of Things edge devices

Abstract

The performance of the Internet of Things (IoT) devices is gradually improving. However, traditional memory devices cannot meet the requirements of IoT devices in terms of energy consumption, capacity, I/O efficiency, and so on. This paper proposed a hybrid storage class memory architecture, which uses phase-change memory (PCM) and dynamic random-access memory (DRAM) to form a hybrid structure that is managed by a hybrid memory controller and an in-memory file system. A dynamic page row buffer miss migration (DPRM) algorithm is proposed to optimize for hybrid memory to reduce the negative impact on PCM. A wear-leveling scheme is added to the persistent in-memory file system to make the write access in PCM more dispersed, improving the reliability of the storage system. Experimental results show that the energy consumption of the memory system can be reduced by 47.57%, and the I/O efficiency has increased by 9.57 times when compared to the traditional memory systems of IoT devices.