Warpage Of Printed Wiring Board Research Articles

Comparison of Warpage Measurement Capabilities and Results Obtained by Using Laser and Digital Fringe Projection Methods

Electronic packaged devices are becoming increasingly smaller in size and higher in density while requiring higher performance and superior reliability. Warpage is one of the crucial factors for the thermomechanical reliability of electronic packages and warpage control becomes a more crucial process during the printed wiring board (PWB) fabrication and package assembly processes. This requirement necessitates more accurate methods of measuring warpage. The fringe projection methods are recent trends for measuring the warpage of chip packages, PWBs, and PWB assemblies (PWBAs) because of their noncontact, full-field, and high-resolution measurement capabilities. This paper presents a comparison of two fringe projection methods: laser fringe projection (LFP) (projection moiré) and digital fringe projection (DFP). Experimental results show that digital fringe projection has higher practical resolution, and better accuracy and precision than laser fringe projection.

Techniques for Measuring Warpage of Chip Packages, PWBs, and PWB Assemblies

One of the crucial factors for the thermo-mechanical reliability of electronic packages is warpage that occurs during the printed wiring board (PWB) fabrication, solder masking and solder reflow processes. As the quality and reliability requirements of electronic components (packages) become higher, warpage control becomes a more crucial process during the PWB fabrication (manufacturing) and package assembly processes. The warpage of PWBs, PWB assemblies and electronic packages are measured by various techniques. Each technique has both its advantages and disadvantages; therefore the choice of a particular technique depends on whether one wants to measure the warpage of a PWB, PWB assembly or chip package. This paper reviews the pros and cons, such as resolution, speed, costs, accuracy, in-line capability, flexibility, and robustness, of different techniques used for measuring the warpage of chip packages, PWBs and PWB assemblies.

Effects of Warpage on Fatigue Reliability of Solder Bumps: Experimental and Analytical Studies

Out-of-plane displacement (warpage) has been a major thermomechanical reliability concern for board-level electronic packages. Printed wiring board (PWB) and component warpage results principally from coefficient of thermal expansion mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to severe solder bump reliability problems. In this research, the effect of initial PWB warpage on the low cycle thermal fatigue reliability of the solder bumps in plastic ball grid array (PBGA) packages was studied using experimental and analytical methods. A real-time projection moire? warpage measurement system was used to measure the surface topology of PWBA samples at different temperatures. The thermal fatigue reliability of solder bumps was evaluated from experimental thermal cycling tests and finite element simulation results. Three-dimensional (3-D) models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moire? method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the finite element method. The simulation results were validated and correlated with the experimental results obtained using the projection moire? technique and accelerated thermal cycling tests. An advanced prediction model was generated to predict board level solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials.

A Novel Projection Moiré System for Measuring PWBA Warpage Using Simulated Optimized Convective Reflow Process

The shadow moiré technique is a widely used method of measuring printed wiring board (PWB) warpage. It has a high resolution, high accuracy, and is suitable for use in an online environment. The shortcoming of the shadow moiré technique is that it cannot be used to measure PWBs populated with chip packages. In this paper, a novel warpage measurement system based on the projection moiré technique is presented. The system can be used to measure bare PWBs, as well as PWBs populated with chip packages. In order to use the projection moiré system to accurately determine the warpage of PWBs and chip packages separately, an automated chip package detection algorithm based on active contours is utilized. Unlike the shadow moiré technique, which uses a glass grating, the projection moiré technique uses a virtual grating. The virtual grating sizes can be adjusted, making it versatile for measuring various PWB and chip package sizes. Without the glass grating, which is a substantial heat inertia, the PWB/printed wiring board assembly (PWBA) sample can be heated more evenly during the thermal process. The projection moiré system described in this paper can also be used to measure the warpage of PWBs/PWBAs/chip packages during convective reflow processes. In this paper, the characteristics of the projection moiré warpage measurement system will be described. In addition, the system will be used to measure the warpage of a PWB and plastic ball grid array packages during a Lee optimized convective reflow process (Lee, N.-C., 2002, Reflow Soldering Processes and Troubleshooting SMT, BGA, CSP, and Flip Chip Technologies, Butterworth-Heinemann, MA). It is concluded that this projection moiré warpage measurement system is a powerful tool to study the warpage of populated PWBs during convective reflow processes.

Simultaneous Measurement of PWB and Chip Package Warpage Using Automatic Image Segmentation

The shadow moire and projection moire techniques are widely used methods for measuring printed wiring board (PWB) and PWB assembly (PWBA) warpage. Both methods have high resolution, high accuracy and are suitable for use in an online environment. When measuring the warpage of a bare PWB, maximum warpage across the PWB is calculated by subtracting the minimum out-of-plane displacement on the PWB from the maximum out-of-plane displacement on the PWB. However, when the PWB is populated with electronic components (chip packages); the difference between the maximum and minimum out-of-plane displacements on the PWBA is not the warpage of the PWB or the warpage of the chip packages. In order to use warpage measurement methods such as the shadow and projection moire techniques to accurately and separately determine the warpage of a PWB and chip packages in a PWBA, an automated chip package segmentation algorithm is developed and will be presented in this paper. The automated algorithm is based on active contour models (snakes) and can be used to detect chip package locations on an out-of-plane displacement image of a PWBA. This paper will discuss the characteristics of the automated algorithm, which is applicable to all warpage measurement methods, not just the out-of-plane moire methods. Warpage case studies of PWBs populated with plastic ball grid array chip packages measured using the projection moire technique will also be presented and will show that the developed algorithm along with a warpage measurement method is a powerful tool for measuring the warpage of populated PWBs.

Fatigue Assessment of Solder Bumps on Board Assemblies Affected by PWB Warpage

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly processes and normal operations may lead to severe solder bump failures. In this research, the effect of PWB warpage on the low cycle fatigue of the solder bumps in plastic ball grid array (PBGA) packages was studied. Finite element modeling (FEM) was used for the strain-based life prediction of solder bumps on board assemblies. In this paper, 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moiré method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The PWBAs with known PWB warpage were modeled to determine the influence of various levels of initial PWB warpage on the low cycle fatigue failure of solder bumps. The effect of different types of PBGAs with varying locations on solder bump fatigue was studied. Both Sn-Pb and lead-free solder materials were used in this study. The FE models were validated with experimental results obtained using the projection moiré technique. The FE results showed that the initial PWB warpage has significant a effect on the fatigue reliability of solder bumps in PBGA packages.